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      MLE and Trenz Verify the AMD Versal™ AI Edge Device and Accelerate Networking and Storage with 10G/25G/50G/100G TCP/IP Core

      MLE and Trenz Electronic, both Premier Members of the AMD Adaptive Computing Partner Program, have collaborated and worked on Trenz’s new TE0950 AMD Versal™ AI Edge Evalboard to provide an integrated and pre-validated network and storage accelerating solution.

      To realize network acceleration with AMD Versal™ AI Edge device, MLE implements the latest version of the TCP/IP Network Protocol Accelerator Platform which gains enhancements for performance and interoperability, on the TE0950 AMD Versal™ AI Edge Evalboard. Currently the 10G/25G TCP/IP Core is verified on the board in the Linux system, and testing with 50G/100G TCP/IP Core is also scheduled.

      MLE also tested Opsero’s FPGA Drive FMC Gen4 with our NVMe Streamer, the full accelerator NVMe host subsystem, to enable high read/write bandwidth for SSD mass storage connectivity. We implement and verify a single PCIe x4 Gen4 SSD with 16GT/s transfer rate on the TE0950 AMD Versal™ AI Edge Evalboard.

      MLE is dedicated to de-risking system design via integration and development services and FPGA Full System Stacks. Through testing in the MLE lab, we can verify the compatibility between Trenz’s new TE0950 board and our IP-core accelerators and its performance in accelerating networking and storage. 

      If you are interested in the Trenz’s TE0950 AMD Versal™ AI Edge Evalboard integrated with MLE’s 10G/25G/50G/100G TCP/IP Network Protocol Accelerator Platform or NVMe Streamer, please contact us for more information and evaluation.

      How Bad is TCP? (And What Are the Alternatives?)

      Presentation at SNIA Storage Developers Conference, Fremont, CA, Sept. 18-21, 2023

      Tail latencies in networking tend to worry us all, whether we implement distributed storage and compute or whether we connect systems-of-systems in automotive or factory automation, for example. Same goes for the computational burden of processing networking protocols.

      One of the foundations of reliable networking is TCP, the Transmission Control Protocol which was introduced half a century ago. Today, TCP is ubiquitous: In the data center, in mobile communication, the Internet and in (embedded) systems-of-systems. However, TCP has some significant drawbacks including unpredictable tail latency and a significant computational burden.

      This presentation aims to guide engineers in their systems design by sharing quantitative analysis results and describing alternatives. For latency analysis we present benchmarks results from network simulation which show the significant tail latencies for TCP. We also share benchmark results from running TCP implementations of different Linux kernels – with sometimes surprising outcomes.

      Benchmarks for the computational burden extend our analysis of implementations of TCP processing in various Linux kernels. We discuss a metric for Efficiency as in Throughput per CPU load and compare results.

      Finally, we present Homa from John Ousterhout’s team at Stanford University. Homa is an implementation of a so-called Quad-RP, i.e. Rapid, Reliable Request-Response Protocol: Instead of streams it is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized architectures. It puts the recipients in control which enables proactive approaches to congestion control and thereby achieves better network infrastructure utilization. While not TCP API compatible, overall, Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks.

      We close with an outlook of the potential realizations in ASIC and FPGA to enable energy – efficient, deterministic networking as well as potential use in networked storage.

      SNIA Storage Developers Conference, Sept. 18-21, 2023 in Fremont, CA

      The Storage Developers Conference (SDC) 2023 of SNIA, the Storage and Networking Industry Alliance, will be held Sept. 18-21 in Fremont, CA.

      There, MLE will present “How Bad is TCP? (And What Are the Alternatives?)“. TCP is ubiquitous, however, it has some significant drawbacks including unpredictable tail latency and a significant computational burden. MLE will share quantitative analysis results and describing alternatives.

      One of which is the “Homa” protocol from John Ousterhout’s team at Stanford University. Homa is an implementation of a so-called Quad-RP, i.e. Rapid, Reliable Request-Response Protocol: Instead of streams it is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized architectures.

      MLE Joins the EtherCAT Technology Group

      EtherCAT, the Ethernet Fieldbus, is the open real-time Ethernet network originally developed by Beckhoff. EtherCAT sets new standards for real-time performance and topology flexibility.

      Nick-named “Robo/TSN”, MLE is extending its patented and patent pending technology to provide industrial, medical, and robotics networking solutions combining high-accuracy time-synchronization with high data rates of 100 Gbps, and faster. Robo/TSN will be capable of interfacing with, and tunneling of, EtherCAT.

      FPGA Drives Next-gen Automatic Test Equipment

      Advantest is a world-class manufacturer of advanced automatic test equipment (ATE) for the semiconductor industry. Missing Link Electronics (MLE) has been involved in our advanced FPGA design efforts over several different tester models. 

      In 2021 and 2022 we engaged MLE to help in supporting the development of PCIe Gen 5 and NVMe interface on our ATE systems.

      The MLE engineers that were assigned to work with us were experienced and very knowledgeable.

      They coordinated with our internal team extremely well and were able to deliver working designs on-time and within budget.


      Corundum DPDK Driver

      MLE presents an initial DPDK driver for the corundum multi-queue network interface card (mqnic). The driver is available via the respective github repository of Missing Link Electronics.

      DPDK is the acronym for Data Plane Development Toolkit and it consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures. To enable packet reception and transmission, a driver is required to integrate various NICs into the DPDK.

      Corundum mqnic is a project aiming at providing a fully open source FPGA based in network compute platform, comprising Linux drivers and gateware supporting various FPGA vendors, families and devices.

      The Missing Link Electronics DPDK Driver for the Corundum mqnic now enables a fully open source development environment for high-performance network processing research. This may involve new hardware software partitioning as, for the first time, both the hardware and the software side are available as open source.

      The driver is available for multiple dpdk-stable versions 22.11, 21.11 and 20.11 and supports multiple interfaces per device. It has been tested against corundum version 0965c77 using a ZCU106 implementation featuring 2x 10 GbE interfaces and a custom Fidus Sidewinder-100 implementation featuring 8x 10G interfaces. The tests are based on the DPDK forwarding example and an iperf client and server running on two additional machines, connected to one of the network interfaces implemented by corundum, each.

      Berlin 6G Conference

      Berlin 6G Conference is the annual networking event of the German 6G Program, organized by the 6G Platform Germany, will take place at the Berlin Congress Center (BCC) from June 27-29, 2023.

      The 6G Platform Germany is an R&D initiative with a total funding of €700 million. One of the core topics is the combination of a secure radio and sensing, so-called Integrated Communication and Sensing (ICAS) with aims to develop such a combination for communication and sensing of the environment and to integrate it into a joint system for the future mobile radio standard 6G.

      MLE actively contributes to the 6G-ICAS4Mobility project.

      Trenz Electronic GmbH and Missing Link Electronics, Inc. Enter Strategic Partnership to Deliver Turnkey Solutions and Full System Stacks with FPGA

      Trenz Electronic GmbH (Trenz), Hüllhorst, Germany, and Missing Link Electronics, Inc. (MLE), San Jose, CA, both Premier Members of the AMD Adaptive Computing Partner Program, have entered a strategic partnership to provide FPGA-based Turnkey Solutions and Full System Stacks, extending their European collaboration to Canada and the United States. 

      The market for Field-Programmable Gate Arrays (FPGA) continues to grow significantly owing to its increasing performance, flexibility, cost and energy benefits in various end-use industries: Automotive, Aerospace/Defence, Industrial/Scientific/Medical, Compute, Wired and Wireless Telecommunication. However, the difficulty in programming FPGAs, in particular those System-on-Chip (SoC) FPGA with embedded CPUs, has long been considered a disadvantage that prevents FPGA from becoming a general computation solution. Integrated and pre-validated building blocks such as Trenz’ System-on-Modules (SoM) FPGA hardware and MLE’s Compute, Video, Storage and Networking FPGA software subsystems significantly increase the productivity of end-users of FPGAs while shortening time-to-market for new product initiatives.

      The aim of this strategic partnership is to de-risk and to cost-down High-Performance Compute and Embedded Systems by delivering complete FPGA Turnkey Solutions and Full System Stacks to end users in volume.

      Trenz and MLE have established close engineering collaboration and a track record of shipping integrated FPGA solutions based on Trenz SoM running MLE’s System Software Stacks with Compute, Video, Storage and/or Network Acceleration. Given MLE’s presence in the heart of Silicon Valley, this new level of partnership gives customers in the USA and Canada easy access to FPGA-based cards, boards, SoMs from Trenz along with IP Cores, design services and engineering support from MLE experts. 

      A 40 GigE SD-WAN Access Point and Customer Premise Equipment – which is now shipping to a green-field telco customer in Canada – is a typical example of this close partnership: To de-risk the project, MLE started with the AMD Zynq UltraScale+ MPSoC on the Trenz SoM TE0808 within a Trenz Starter Kit and could deliver a working Proof-of-Concept within weeks. Based on this success, MLE modified the Trenz carrierboard TEBF0808 to meet the customer’s connectivity requirements. Again, manufactured by Trenz Electronic Manufacturing Services (EMS), the first product shipped within less than a year. For volume ramp-up Trenz and MLE are planning a so-called chip-down solution (unifying the SoM with the baseboard to a single PCB) which maintains key system/software compatibility but shrinks the hardware Bill-of-Materials (BoM) costs. 

      About Trenz

      Since 1992 Trenz Electronic has operated as a provider of development and production services for the electronics industry. Services include design-in support as well as turnkey designs which typically covers all steps from product specification, hard- and software design up to prototyping and production. Trenz specializes in the design of high-speed data acquisition, high-accuracy measurement and embedded digital signal processing systems based on FPGA and CPU architectures. Trenz development service is supplemented by FPGA-and MCU-based development boards and tools.

      About MLE

      Head-quartered in Silicon Valley with engineering offices in Berlin and Neu-Ulm, Germany, Missing Link Electronics (MLE) has successfully delivered solutions for Wired and Wireless Telecommunications, Datacenter storage, network protocol and algorithm acceleration in the cloud, Autonomous Driving and ADAS and Image processing and sensor fusion with camera, Radar, Lidar sensors etc.