{"version":"1.0","provider_name":"MLE Developer Zone","provider_url":"https:\/\/www.missinglinkelectronics.com\/devzone","author_name":"Yi-Ying Li","author_url":"https:\/\/www.missinglinkelectronics.com\/devzone\/author\/yiying\/","title":"FPGA Design Integration - MLE Developer Zone","type":"rich","width":600,"height":338,"html":"<blockquote class=\"wp-embedded-content\" data-secret=\"HbytFBRqhf\"><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-fpga-design-integration\/\">FPGA Design Integration<\/a><\/blockquote><iframe sandbox=\"allow-scripts\" security=\"restricted\" src=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-fpga-design-integration\/embed\/#?secret=HbytFBRqhf\" width=\"600\" height=\"338\" title=\"&#8220;FPGA Design Integration&#8221; &#8212; MLE Developer Zone\" data-secret=\"HbytFBRqhf\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" class=\"wp-embedded-content\"><\/iframe><script type=\"text\/javascript\">\n\/* <![CDATA[ *\/\n\/*! This file is auto-generated *\/\n!function(d,l){\"use strict\";l.querySelector&&d.addEventListener&&\"undefined\"!=typeof URL&&(d.wp=d.wp||{},d.wp.receiveEmbedMessage||(d.wp.receiveEmbedMessage=function(e){var t=e.data;if((t||t.secret||t.message||t.value)&&!\/[^a-zA-Z0-9]\/.test(t.secret)){for(var s,r,n,a=l.querySelectorAll('iframe[data-secret=\"'+t.secret+'\"]'),o=l.querySelectorAll('blockquote[data-secret=\"'+t.secret+'\"]'),c=new RegExp(\"^https?:$\",\"i\"),i=0;i<o.length;i++)o[i].style.display=\"none\";for(i=0;i<a.length;i++)s=a[i],e.source===s.contentWindow&&(s.removeAttribute(\"style\"),\"height\"===t.message?(1e3<(r=parseInt(t.value,10))?r=1e3:~~r<200&&(r=200),s.height=r):\"link\"===t.message&&(r=new URL(s.getAttribute(\"src\")),n=new URL(t.value),c.test(n.protocol))&&n.host===r.host&&l.activeElement===s&&(d.top.location.href=t.value))}},d.addEventListener(\"message\",d.wp.receiveEmbedMessage,!1),l.addEventListener(\"DOMContentLoaded\",function(){for(var e,t,s=l.querySelectorAll(\"iframe.wp-embedded-content\"),r=0;r<s.length;r++)(t=(e=s[r]).getAttribute(\"data-secret\"))||(t=Math.random().toString(36).substring(2,12),e.src+=\"#?secret=\"+t,e.setAttribute(\"data-secret\",t)),e.contentWindow.postMessage({message:\"ready\",secret:t},\"*\")},!1)))}(window,document);\n\/\/# sourceURL=https:\/\/www.missinglinkelectronics.com\/devzone\/wp-includes\/js\/wp-embed.min.js\n\/* ]]> *\/\n<\/script>\n","description":"FPGA Design Integration of MLE NPAP MLE NPAP is available as VHDL RTL source code or as a netlist suitable for synthesis by 3rd party and FPGA vendor tools which makes it possible to support almost any FPGA or ASIC target platform. The following toolchain versions have been tested at MLE: Version AMD\/Xilinx Altera\/Intel LatticeRead More","thumbnail_url":"https:\/\/www.missinglinkelectronics.com\/devzone\/wp-content\/uploads\/2026\/08\/image-11-1024x633.png"}