{"id":7847,"date":"2026-08-18T07:38:53","date_gmt":"2026-08-18T14:38:53","guid":{"rendered":"https:\/\/www.missinglinkelectronics.com\/devzone\/?page_id=7847"},"modified":"2026-09-09T02:10:57","modified_gmt":"2026-09-09T09:10:57","slug":"npap-datasheet","status":"publish","type":"page","link":"https:\/\/www.missinglinkelectronics.com\/devzone\/npap-datasheet\/","title":{"rendered":"NPAP Datasheet"},"content":{"rendered":"\n<div class=\"wp-block-group ticss-0a4f9d55 has-background is-vertical is-layout-flex wp-container-core-group-is-layout-8cf370e7 wp-block-group-is-layout-flex\" style=\"background-color:#3ba7d91c\">\n<h2 class=\"wp-block-heading\" id=\"TCP\/UDP\/IPv4_NPAP_Datasheet\" style=\"font-size:40px\"><strong>Network Protocol Accelerator Platform (NPAP)<\/strong><\/h2>\n\n\n\n<p style=\"font-size:26px\">TCP\/UDP\/IPv4 Accelerators for Multi-Gigabit Ethernet<\/p>\n<\/div>\n\n\n\n<div style=\"height:50px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:25%\">\n<p class=\"ticss-9e562a51\">NPAP Datasheet<\/p>\n\n\n<ul><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-overview\/\">Overview<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-key-features\/\">Key Features<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-technical-specifications\/\">Technical Specifications<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-latency-analysis-results\/\">Latency Analysis Results<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-ip-core-deliverables\/\">IP-Core Deliverables<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-developer-documentation\/\">Developer Documentation<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-benchmarking-using-netperf\/\">Benchmarking using Netperf<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-implementation-details\/\">Implementation Details<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-dataflow-block-diagram\/\">Dataflow Block Diagram<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-control-flow-view\/\">Control-Flow View<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-diagnostics-and-network-statistics\/\">Diagnostics and Network Statistics<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-network-impairment-bit-error\/\">Network Impairment (Bit Errors)<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-fpga-resource-estimates\/\">FPGA Resource Estimates<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-changelog\/\">Changelog<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-protocol-support-rfc1122\/\">Protocol Support (RFC1122)<\/a><\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<p class=\"ticss-9e562a51\">NPAP Architecture<\/p>\n\n\n<ul><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-system-level-architecture-aspects\/\">System-Level Architecture Aspects<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-picking-the-right-tcp-peer\/\">Picking the \u201cRight\u201d TCP Peer<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-tcp-rx-tx-buffer-sizes\/\">TCP Rx\/Tx Buffer Sizes<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-scaling-the-number-of-tcp-cores\/\">Scaling the Number of TCP Cores<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-optimize-for-performance\/\">Optimize for Performance<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-hybrid-acceleration\/\">Hybrid Acceleration<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-linux-kernel-bypass\/\">Linux Kernel Bypass<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-time-sensitive-networking-tsn\/\">Time-Sensitive Networking (TSN)<\/a><\/li><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-transport-layer-security-tls\/\">Transport Layer Security (TLS)<\/a><\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<p class=\"ticss-471be96a\">NPAP PCB Design<\/p>\n\n\n<ul><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-fpga-design-integration\/\">FPGA Design Integration<\/a><\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<p class=\"ticss-471be96a\">NPAP System Verification<\/p>\n\n\n<ul><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-rtl-simulation-and-verification\/\">RTL Simulation and Verification<\/a><\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<p class=\"ticss-277483cd\">NPAP Network Admin<\/p>\n\n\n<ul><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-network-administration\/\">Network Administration<\/a><\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity is-style-default\"\/>\n\n\n\n<p class=\"ticss-c58110be\">NPAP Evaluation<\/p>\n\n\n<ul><li><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-evaluation-choices\/\">Evaluation Choices<\/a><\/li><\/ul>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<div style=\"height:5px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:75%\">\n<h2 class=\"wp-block-heading\">NPAP Summary<\/h2>\n\n\n\n<p>MLE\u2019s <a href=\"https:\/\/www.missinglinkelectronics.com\/ip-cores\/npap-tcp-udp-ip-stack\/\" data-type=\"link\" data-id=\"https:\/\/www.missinglinkelectronics.com\/ip-cores\/npap-tcp-udp-ip-stack\/\">Network Protocol Accelerator Platform (NPAP)<\/a> is a proven TCP\/UDP\/IPv4 network protocol Full-Accelerator to enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G \/ 2.5G \/ 5G \/ 10G \/ 25G \/ 40G \/ 50G \/ 100G \/ 400G Ethernet links.<\/p>\n\n\n\n<p>Here you can find further technical details of MLE&#8217;s NPAP solutions, including:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-overview\/\" data-type=\"post\" data-id=\"7868\">NPAP Datasheet<\/a><\/strong><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-architecture\/npap-system-level-architecture-aspects\/\" data-type=\"post\" data-id=\"8017\">NPAP Achitecture<\/a><\/strong><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-evaluation\/npap-evaluation-choices\/\" data-type=\"post\" data-id=\"7971\">NPAP Evaluation<\/a><\/strong><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-pcb-design\/npap-fpga-design-integration\/\" data-type=\"post\" data-id=\"8061\">NPAP PCB Design<\/a><\/strong><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-network-administration\/\" data-type=\"post\" data-id=\"8118\">NPAP Network Administration<\/a><\/strong><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-rtl-simulation-and-verification\/\" data-type=\"post\" data-id=\"8125\">NPAP System Verification<\/a><\/strong><\/li>\n<\/ul>\n\n\n\n<div style=\"height:20px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<hr class=\"wp-block-separator has-text-color has-alpha-channel-opacity has-background\" style=\"background-color:#e6e6e6;color:#e6e6e6\"\/>\n<\/div>\n<\/div>\n\n\n\n<div style=\"height:50px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Network Protocol Accelerator Platform (NPAP) TCP\/UDP\/IPv4 Accelerators for Multi-Gigabit Ethernet NPAP Datasheet NPAP Architecture NPAP PCB Design NPAP System Verification NPAP Network Admin NPAP Evaluation NPAP Summary MLE\u2019s Network Protocol Accelerator Platform (NPAP) is a proven TCP\/UDP\/IPv4 network protocol Full-Accelerator to enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G \/ 2.5G<\/p>\n<p class=\"more-link\"><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/npap-datasheet\/\" class=\"themebutton\">Read More<\/a><\/p>\n","protected":false},"author":5,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_themeisle_gutenberg_block_has_review":false,"footnotes":""},"categories":[163],"tags":[31],"class_list":["post-7847","page","type-page","status-publish","hentry","category-datasheet","tag-npap"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>TCP\/UDP\/IPv4 NPAP Datasheet - MLE Developer Zone<\/title>\n<meta name=\"description\" content=\"MLE\u2019s Network Protocol Accelerator Platform (NPAP) is a proven TCP\/UDP\/IPv4 network protocol Full-Accelerator to enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G \/ 2.5G \/ 5G \/ 10G \/ 25G \/ 40G \/ 50G \/ 100G \/ 400G Ethernet links.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, 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