{"id":6529,"date":"2021-12-15T05:56:58","date_gmt":"2021-12-15T13:56:58","guid":{"rendered":"https:\/\/www.missinglinkelectronics.com\/?p=6529"},"modified":"2024-06-19T02:12:50","modified_gmt":"2024-06-19T09:12:50","slug":"picking-the-right-granularity-when-buffering-pcie-nvme-data","status":"publish","type":"post","link":"https:\/\/www.missinglinkelectronics.com\/devzone\/fpga-devtips\/picking-the-right-granularity-when-buffering-pcie-nvme-data\/","title":{"rendered":"Picking The Right Granularity When Buffering PCIe\/NVMe Data"},"content":{"rendered":"Picking The Right Granularity When Buffering PCIe\/NVMe Data Table of ContentsPicking The Right Granularity When Buffering PCIe\/NVMe DataBlockRAM (BRAM)UltraRAM (URAM)DDRx DRAMHigh Bandwidth Memory (HBM2)Conclusion Non-Volatile Memory Express (NVMe) is an interface specification often used with PCIe. Its goal is to leverage the parallelism and low latency of modern SSDs. A typical PCIe payload data transfer happens in data chunks of either 128 Byte or 256 Byte. SSDs deploy several tricks (wear leveling, SLC to TLC conversion) to enhance the read and write speeds as well as their lifespan. One downside is that their read and write speed is not constant over a long write\/read period which might result in backpressure. Some applications do not support back pressure that can lead to an erroneous state if one employs a standard SSD system.&nbsp;&nbsp; One possible mitigation strategy is to have an elastic buffer between the SSD and the data source.&nbsp; Using an FPGA, there are different possibilities to implement an elastic buffer. At MLE, we investigated BlockRAM (BRAM), UltraRAM (URAM), Dynamic RAM (DRAM) and the second generation of High Bandwidth Memory&nbsp; (HBM2). Each memory technology has its advantages and disadvantages regarding its capabilities to handle different data chunk sizes.&nbsp; We will present our findings below.&nbsp; BlockRAM (BRAM) BRAM is a RAM module which can<p class=\"more-link\"><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/fpga-devtips\/picking-the-right-granularity-when-buffering-pcie-nvme-data\/\" class=\"themebutton\">Read More<\/a><\/p>","protected":false},"excerpt":{"rendered":"<p>Picking The Right Granularity When Buffering PCIe\/NVMe Data Non-Volatile Memory Express (NVMe) is an interface specification often used with PCIe. Its goal is to leverage the parallelism and low latency of modern SSDs. A typical PCIe payload data transfer happens in data chunks of either 128 Byte or 256 Byte. SSDs deploy several tricks (wear<\/p>\n<p class=\"more-link\"><a href=\"https:\/\/www.missinglinkelectronics.com\/devzone\/fpga-devtips\/picking-the-right-granularity-when-buffering-pcie-nvme-data\/\" class=\"themebutton\">Read More<\/a><\/p>\n","protected":false},"author":10,"featured_media":6909,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_themeisle_gutenberg_block_has_review":false,"footnotes":""},"categories":[98,107],"tags":[74,79,80,81,82,83,42],"class_list":["post-6529","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-fpga-devtips","category-storage-acceleration","tag-amd-xilinx-zcu106","tag-bram","tag-dram","tag-hbm2","tag-high-bandwidth-memory-hbm2","tag-memory-combination","tag-pci-express"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Picking The Right Granularity When Buffering PCIe\/NVMe Data<\/title>\n<meta name=\"description\" content=\"To keep SSD read\/write speed constant over a long period, FPGA can implement an elastic buffer efficiently. See MLE&#039;s discovery on DRAM, URAM, BRAM and more.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/devzone.missinglinkelectronics.com\/fpga-devtips\/picking-the-right-granularity-when-buffering-pcie-nvme-data\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Picking The Right Granularity When Buffering PCIe\/NVMe Data\" \/>\n<meta property=\"og:description\" content=\"To keep SSD read\/write speed constant over a long period, FPGA can implement an elastic buffer efficiently. See MLE&#039;s discovery on DRAM, URAM, BRAM and more.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/devzone.missinglinkelectronics.com\/fpga-devtips\/picking-the-right-granularity-when-buffering-pcie-nvme-data\/\" \/>\n<meta property=\"og:site_name\" content=\"MLE Developer Zone\" \/>\n<meta property=\"article:published_time\" content=\"2021-12-15T13:56:58+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2024-06-19T09:12:50+00:00\" \/>\n<meta name=\"author\" content=\"Anna Schreiber\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Anna Schreiber\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"TechArticle\",\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/\"},\"author\":{\"name\":\"Anna Schreiber\",\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/#\\\/schema\\\/person\\\/3a5fb3e900ec94113fa75dbc15d91bfe\"},\"headline\":\"Picking The Right Granularity When Buffering PCIe\\\/NVMe Data\",\"datePublished\":\"2021-12-15T13:56:58+00:00\",\"dateModified\":\"2024-06-19T09:12:50+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/\"},\"wordCount\":714,\"image\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.missinglinkelectronics.com\\\/devzone\\\/wp-content\\\/uploads\\\/2021\\\/12\\\/technology-background-texture.jpg\",\"keywords\":[\"AMD\\\/Xilinx ZCU106\",\"BRAM\",\"DRAM\",\"HBM2\",\"High Bandwidth Memory (HBM2)\",\"Memory Combination\",\"PCI Express\"],\"articleSection\":[\"FPGA DevTips\",\"Storage Acceleration\"],\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/\",\"url\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/\",\"name\":\"Picking The Right Granularity When Buffering PCIe\\\/NVMe Data\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/fpga-devtips\\\/picking-the-right-granularity-when-buffering-pcie-nvme-data\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.missinglinkelectronics.com\\\/devzone\\\/wp-content\\\/uploads\\\/2021\\\/12\\\/technology-background-texture.jpg\",\"datePublished\":\"2021-12-15T13:56:58+00:00\",\"dateModified\":\"2024-06-19T09:12:50+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/devzone.missinglinkelectronics.com\\\/#\\\/schema\\\/person\\\/3a5fb3e900ec94113fa75dbc15d91bfe\"},\"description\":\"To keep SSD read\\\/write speed constant over a long period, FPGA can implement an elastic buffer efficiently. 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