{"id":7871,"date":"2026-08-10T06:56:37","date_gmt":"2026-08-10T13:56:37","guid":{"rendered":"https:\/\/www.missinglinkelectronics.com\/devzone\/?p=7871"},"modified":"2026-09-07T05:11:16","modified_gmt":"2026-09-07T12:11:16","slug":"npap-technical-specifications","status":"publish","type":"post","link":"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap_datasheet\/npap-technical-specifications\/","title":{"rendered":"Technical Specifications"},"content":{"rendered":"MLE NPAP Technical Specifications FeatureSpecificationSupported on-chip Interfaces128 bit wide AXI4-StreamCompatibility with 3rd party Ethernet PHY interfacesStandard IEEE Ethernet PHYs with RMII, GMII, XGMII, etc via PCS\/PMA via ASIC\/FPGA Ethernet SubsystemCompatibility with 3rd party Ethernet Media Access ControllersFraunhofer HHI 10G\/25G Low-Latency MACAMD\/Xilinx 10G\/25G Ethernet Subsystem (PG210)AMD\/Xilinx 100G Ethernet Subsystem (PG165, PG203, PG314)Altera 10G \/ 25G Ethernet FPGA IPMicrochip PolarFire FPGA 10G Ethernet (UG0727)Lattice 10G \/ 25G Ethernet IP (FPGA-IPUG-02245)Supported protocols (Hardware based)Ethernet, ARP, IPv4, ICMPv4 (response only), IGMPv4, UDP & TCP, DHCP (client only)Number of simultaneous connectionsOne per TCP Core instantiation – see \u201cArchitecture Choices\u201d below, a TCP Core in NPAP relates to a TCP socket in LinuxMessage SizesSupport for Ethernet Jumbo Frames of arbitrary lengthInterface to applicationDatapath via AXI4-Stream 128-bitand separate custom TCP command interfaceSupported FPGAs  Complete stack uses generic VHDL code (IEEE-1076 2002 or 2008, depending on NPAP version)AMD\/Xilinx Virtex 4 to Virtex UltraScale+AMD\/Xilinx Kintex to Kintex UltraScale+AMD\/Xilinx Artix UltraScale+AMD\/Xilinx Zynq-7000AMD\/Xilinx Zynq UltraScale+ MPSoCAMD\/Xilinx Zynq UltraScale+ RFSoCAMD\/Xilinx Versal ACAP SeriesAMD Versal Gen2Altera Cyclone IV seriesAltera Cyclone 10 GX seriesAltera Stratix VAltera Stratix 10 GX seriesAltera Agilex 5 D, E SeriesAltera Agilex 7 F, I, M SeriesLattice Avant-G, Avant-XMicrochip Polarfire and PolarFire SoCPerformance70 Gbps line rate, or faster, for single TCP\/IPv4 session (depending on clock rate, see below)Typ. 500 ns transport delay

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MLE NPAP Technical Specifications Feature Specification Supported on-chip Interfaces 128 bit wide AXI4-Stream Compatibility with 3rd party Ethernet PHY interfaces Standard IEEE Ethernet PHYs with RMII, GMII, XGMII, etc via PCS\/PMA via ASIC\/FPGA Ethernet Subsystem Compatibility with 3rd party Ethernet Media Access Controllers Fraunhofer HHI 10G\/25G Low-Latency MACAMD\/Xilinx 10G\/25G Ethernet Subsystem (PG210)AMD\/Xilinx 100G Ethernet Subsystem<\/p>\n

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