{"id":7971,"date":"2026-08-10T06:52:52","date_gmt":"2026-08-10T13:52:52","guid":{"rendered":"https:\/\/www.missinglinkelectronics.com\/devzone\/?p=7971"},"modified":"2026-09-07T05:52:10","modified_gmt":"2026-09-07T12:52:10","slug":"npap-evaluation-choices","status":"publish","type":"post","link":"https:\/\/www.missinglinkelectronics.com\/devzone\/datasheet\/npap-evaluation-choices\/","title":{"rendered":"Evaluation Choices"},"content":{"rendered":"MLE NPAP Evaluation Choices MLE offers multiple ways to evaluate and benchmark MLE NPAP: A \u201cDevelopers License\u201d is a highly discounted extended evaluation license which gives you full source code access to integrate and run NPAP and NPAP ERDs within your target hardware. Free-of-charge we provide so-called NPAP Evaluation Reference Designs (ERD) implemented on off-the-shelf hardware. These are great for evaluating the functionality and the performance of MLE NPAP, when running in off-the-shelf FPGA hardware. These are also great as a reference design when integrating MLE NPAP into your system. In MLE’s NPAP Evaluation you will find an in depth guide of how to evaluate NPAP using the ERDs. The objective of an ERD is to facilitate design-in via a complete design project running on selected FPGA boards. TCP\/UDP\/IP NPAP Evaluation Design Each ERD typically instantiates the full stack including MAC, Ethernet, IPv4 (with ICMP and IGMP), plus one or more TCP session instances, the UDP block, a Netperf\/Netserver implementation and an Network Impairment generator in programmable logic.  Here some exemplary setups from MLE\u2019s NPAP Test Lab: A more in-depth documentation of the workings of the ERD and the support IPs is available under license. Please contact your MLE sales representative or contact us for more information. Contact Us

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MLE NPAP Evaluation Choices MLE offers multiple ways to evaluate and benchmark MLE NPAP: In MLE’s NPAP Evaluation you will find an in depth guide of how to evaluate NPAP using the ERDs. The objective of an ERD is to facilitate design-in via a complete design project running on selected FPGA boards. Each ERD typically<\/p>\n

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