Missing Link Electronics

MLE Adds IEEE 1735 IP Encryption to XAUI/RXAUI Products

The IEEE Standard 1735-2014 is to protect 3rd party Intellectual Property (IP) Cores used in Electronic Design Automation (EDA) tool chains. In collaboration with Siemens EDA MLE has added cryptography support when simulating the XAUI/RXAUI IP Core in the Questa Advanced Simulator. Early 2021 Xilinx discontinued the XAUI/RXAUI IP Cores and handed over maintenance and support to MLE.

High-Level Synthesis for Intel and Xilinx FPGAs

High-Level Synthesis (HLS) is a formidable way to design Domain Specific Architecture blocks in FPGA and can enable "cross-compilation" between different FPGA device families and FPGA device vendors. Please read "High-Level Synthesis for Intel and Xilinx FPGAs",  Technical Brief MLE-TB20210707, which describes our findings when using HLS to accelerate a telecommunications network protocol accelerator with FPGA. Please read here.

Zone-Based Automotive Backbones Tunneling PCIe

Missing Link Electronics (MLE) announced today that they are partnering with Fraunhofer Heinrich-Hertz-Institute (HHI) and Fraunhofer Institute for Photonic Microsystems (IPMS) on ultra-reliable, deterministic low-latency transports for automotive networks tunneling PCI Express® (PCIe®) architecture.

The need for more safe and eco-friendly vehicles drives automotive connectivity towards so-called Zone-Based Architectures. Inside those so-called Zone Gateways PCIe technology provides the connectivity between multiple System-on-Chip (SoC), CPUs, GPUs, and FPGAs for scalable performance. Within the automotive network, multiple Zone Gateways connect with each other via the emerging IEEE standards “Time Sensitive Networking” (TSN).

Today, Fraunhofer and MLE can provide a working proof-of-concept in form of a digital circuit & system stack which encapsulates and decapsulates PCIe packets (and other protocols) over real-time automotive TSN Ethernet and which scales up to 100 Gbps.

“When we started working on network protocol acceleration in 2010 we looked at future connectivity needs for systems-of-systems such as ships and cars”, states Ulrich Langenbach, formerly with Fraunhofer HHI and now Director Engineering at MLE. “Therefore, our approach does address key topology requirements for modern vehicles which is reliable and cost-efficient PCIe long-range, support for NVMe SSD storage, as well as CPU-to-CPU communication via PCIe Non-Transparent Bridges (NTB)”.

“Our approach of closely adhering to the OSI Layers makes our TSN Switched-Endpoint very interoperable with different Ethernet PHY solutions”, says Marcus Pietzsch, Group Leader IP Cores and ASIC Design at IPMS and emphasizes: “This is vital as the standards and commercial offerings for TSN and for automotive Ethernet are still very fluid!”

“PCI-SIG’s mission is to bring together developers seeking innovation and product compliance around current and future PCIe specifications,” said PCI-SIG President Al Yanes. “The purpose of PCI-SIG’s Automotive Work Group is to facilitate the discussion of PCIe technology in the automotive ecosystem with member companies like MLE.”

Xilinx Adapt EMEA: Automotive, May 18-19, 2021

MLE will present "Zone-Based Architectures with Auto/TSN on Zynq UltraScale+ MPSoC" at the Xilinx Adapt EMEA: Automotive. This is organized as a Virtual Technical Event in the mornings of May 18-19, 2021.

PCI-SIG Virtual Developers Conference 2021

MLE participated as sponsor and as a presenter of "Zone-Based Automotive Backbones Tunneling PCIe" at the PCI-SIG Virtual Developers Conference 2021.

 (download slides) or visit our technical publications

Algoblu partners with MLE on FPGA-Based Network Element Virtualization

Algoblu announced today its Network Element Virtualization (NEV) platform that virtualizes and orchestrates underlying network resources to help carriers offer more application-oriented customized services to both commercial and residential customers. Thanks to the new FPGA-based technology, the cost per bit decreases by more than four times and operation efficiency increases three times.

“We are pleased to collaborate with Algoblu to develop a Network Element Virtualization chip built on leading-edge FPGA technology. The chip is key to Algoblu's NEV architecture with an FPGA-based SMartNIC, all developed in an elegant way,” says Dr. Endric Schubert, CTO at Missing Link Electronics.

MLE joins PCI-SIG Automotive Workgroup

PCI Express (PCIe) has significant advantages which help to drive innovation towards more eco-friendly and safer vehicles. MLE is a member of PCI-SIG and has been providing technology and solutions for PCIe-based Long-Range Tunneling used for automotive backbone connectivity and is proud to volunteer for PCI-SIG's newly formed Automotive Workgroup.

Deterministic Networking with TSN-10/25/50/100G

MLE presents "Deterministic Networking with TCP-TSN-Cores for 10/25/50/100 Gigabit Ethernet" in Technical Brief MLE-TB20201203. Please read here.

US Patent 10,848,442 for Secure Heterogeneous Packet-Based Transport

Missing Link Electronics has been awarded US Patent 10,848,442 on Heterogeneous Packet-Based Transport which covers aspects of secure tunneling packets such as PCI Express (PCIe) Transaction-Layer Packets (TLP) over reliable TCP/IP over 1/10/25/50/100G Ethernet. This extends the range of PCIe and enables building distributed systems based on PCIe.

FPGA-Based Recording to NVMe SSDs

MLE publishes Technical Brief MLE-TB20201012 "Sustained, High-Speed Data Recording with NVMe SSDs" discussing read/write performance aspects of various NVMe SSDs. Please read here.