Presentation at Micro-TCA Workshop at DESY, Hamburg, Germany

Missing Link Electronics presents a way to minimize userspace latencies via hardware-acceleration of networking protocol stacks.
(download slides) or visit our technical publications.


 

 

US Patent 9,209,828 - Configurable Mixed Signal Sxstems

TUE DEC 08 2015

In the area of Mixed Signal Systems, Missing Link Electronics has been awarded US Patent 09,209,828. This patent is titled "Configurable Mixed Signal Systems".

 


 

Presentation at the IHK Erfa-Kreis Embedded Systems in Augsburg

Missing Link Electronics presents examples for the prolonged lifespan of FPGA SoCs and embedded systems in a fast-paced CPU market. 
(download slides) or visit our technical publications.


 

 

Expansion of MLEs workspace

Missing Link Electronics Germany announces doubling of the research and development space in Neu-Ulm. "The newly acquired premises will help us acommodate more staff and equipment to achieve further progress", says Sebastian Stiemke, Director of Engineering.


 

Presentation at the Test-Engineering Day in Neu-Ulm

Missing Link Electronics presents an approach to test the hardware of FPGAs and ASICs during the development stage. MLE would like to thank the Ingenieurbüro Paul Huber for hosting the Test Engineering Day this year. (download slides) or visit our technical publications.


 

Embedded World Exhibition 2015

Fraunhofer HHI and MLE will be available at the Embedded World Exhibition 2015 to discuss benefits of and applications for TCP/UDP/IP Accelerator Technology for FPGAs and ASICs. Please visit us at Booth 4-550 in Hall 4 at the Embedded World Exhibition&Conference 2015.


 

Embedded World Conference 2015

MLE presents "High-Level Synthesis for FPGA Implementation of Network Protocols" - to demonstrate the benefits of using Xilinx Vivado HLS for implementing network protocols and accelerators efficiently in the Zynq All-Programmable SoC. See Session 17/II at the Embedded World Conference 2015.


 

10 GigE Accelerators for TCP/UDP/IP Processing in Zynq-7000

Based on network acceleration technology from German Fraunhofer Heinrich-Hertz-Institute Missing Link Electronics ships Revision 2015.02a of the Evaluation Reference Design for Zynq-7000 All Programmable SOC. Supporting Vivado and Vivado High-Level-Synthesis, this brings full TCP/UDP/IP connectivity for 10 GigE to FPGAs by offloading protocol processing into programmable logic. (More)


 

XPS USB Host Controller Developer's Guide Released

To ease integration of USB Host functionality for FPGA MLE has released the XPS USB Host Controller Developer's Guide. Foundation is the XPS_USB_Host Controller Linux Reference Design from MLE. Using this reference design the various modes of USB can be evaluated based on some basic and easy to reproduce test-cases. This highlights how the XPS_USB_HOST Controller IP Core operates in conjunction with Linux running on an embedded CPU (Xilinx MicroBlaze or PowerPC) inside a Xilinx FPGA device.


 

Release 2.00a for Xilinx USB 2.0 Host Controller

MLE has released Revision 2.00a of the XPS USB 2.0 EHCI Host Controller. Originally from Xilinx, Xilinx handed over service and support to MLE in 2011. The USB 2.0 Host Controller allows users to connect Spartan-6 FPGAs or 7-series FPGAs to full-speed and high-speed USB devices for human-machine interface applications, cameras and storage. An AXI4-based Petalinux reference design ships in Q1, 2015. Please find more information here.