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Frequently Asked Questions

What is Zynq SSE?

Zynq SSE is a turnkey solution and reference design which we intend as one single plug&play SATA host port add-on for Xilinx Zynq when running under Linux.

Is Zynq SSE an IP Core?

While Zynq SSE instantiates IP cores, namely the full ASICS.WS SATA Host Controller and DMA Controller, it is not a soft FPGA IP Core by itself.

Zynq SSE is closer to the other hard IP core I/O functions inside the Zynq Processing System (PS), like UART or SDIO: It is fully instantiated and 'frozen' and cannot be altered - other than you are able to change the pin assignment.

How many SATA ports does Zynq SSE Support?

Zynq SSE supports one (and only one) single SATA Host Port. If you need more, please contact us to discuss other possible solutions. There are several!

I need more than one SATA Port, what shall I do?

Based on our experiences with Xilinx Zynq and SATA, a typical multi-host SATA system comes with certain performance requirements, which most often lean towards an application-specific architecture to deliver such performance.

So, honestly, Zynq SSE cannot do that!

However, we see a couple of options, depending on your project's needs: For example, we can design for you a special multi-host reference design. Or, we can assist you in purchasing the ASICS.WS SATA Host Controller and DMA IP Core.

Please contact us directly to discuss your options.

What is an ERD?

ERD means Evaluation Reference Design. This is a complete compilable Vivado design project comprising an encrypted netlist of the MLE storage micro-architecture, plus all precompiled images, ready-to-run. ERD is a fully functional SATA host which runs for at least 12 hours, until it then times-out. You can request download instructions for an ERD from for testing, free-of-charge.

What is a PRD?

PRD means Production Reference Design which comes in two forms, a PRD-3G for SATA-II and a PRD-6G for SATA-III with support for FPDMA and NCQ. PRD is a Vivado design project comprising an encrypted netlist of the MLE storage micro-architecture. A PRD must be purchased from which gives you the rights to take Zynq SSE into production for one single named project.

What documentation exists for Zynq SSE?

Besides the online documentation listed on our website, as part of each ERD or PRD you will receiv a complete developers guide which explains how to design-in Zynq SSE into your project.

I want to evaluate Zynq SSE, what is the easiest way?

The easiest way is to use the ERD for the Avnet mini-ITX Board which has a SATA header on board. The ERD comes with precompiled binaries. You can request a free-of-charge download from the Request Form on this page.

I want to evaluate Zynq SSE on my own target hardware board, is that possible?

Yes, please contact us and request download instructions for an ERD. ERD comes with a full Vivado design project for you to retarget to and test on your hardware. Please refer to the Zynq SSE Developers Guide of the ERD on how to re-compile. The Developers Guide will also provide information for the SATA capable reference clock to the GTX Clock input (150 MHz, low jitter).

Do I need a License Key for ERD?

No, you will not need any License Key in order to run, or to re-compile, the Zynq SSE ERD.

Do I need a License Key for PRD?

Yes, you will need two License Keys, a Compile-time License Key, and a Run-time License Key:

  • The Compile-time License Key is a Vivado Flex License Key file, tied to the hostid of your design workstation. With this key you can compile the Zynq SSE reference design to add your own design portions, change the SATA pin-out, and to generate bitfiles. We will send you one Compile-time License Key after proof-of-purchase.
  • The Run-time License Key is specific to your Zynq SSE and will disable the time-out mechanism. We will send you one Run-time License Key after proof-of-payment. Please follow the instructions in the MLE Zynq SSE Developers Guide to add this key file to the Linux root filesystem of your Zynq system.

How long will the License Keys be active?

The Compile-time License Key will expire one year after the purchase date. This should be plenty to finish off your design project. The Run-time License Key will never expire.

What does a Zynq SSE PRD include?

Each PRD contains everything you need to extend your Zynq system insert with one single SATA host port: This includes documentation - the so-called Developer's Guide - and a Vivado design project with the ASICS.WS SATA Host Controller and DMA IP-Core inside the MLE microarchitecture and the Linux device drivers. Plus, all the (legal) rights to put those into production for your single, named project.

How much support do I get?

You will receive all reasonable support, typically via Email.

For full functionality of Zynq SSE, do I have to purchase any other licenses?

No. Once you purchase a PRD you will get the Compile-time Key and the Run-time Key to design-in and to operate a fully functional SATA host on Zynq. Our invoice together with the MLE Product License Agreement gives you the legal rights to make and use Zynq SSE for one single named project.

What do you mean with Single-Project-Use?

Without being legalistic here, the single-project-use license allows you use Zynq SSE within the same design project. If you need to fix errors within the FPGA design, or the PCB, and ship a new revision, that would be considered the same project. If you change the device package or re-design the PCB that would probably be another design project. We suggest to follow Xilinx' concept for project based licensing.  Please do not hesitate to contact us if you need clarification.

How long does the PRD work without a Run-time License Key?

Without a purchased Run-time License Key, the SATA link in the PRD will disconnect after 12 hours. Once you have installed the Run-time License Key, this time-out will be disabled.

Does the PRD-3G/6G (with or without a Run-time License Key) have any speed limitations?

No, the PRDs come with full functionality for SATA-II, or SATA-III, respectively.

I have purchased a Zynq SSE PRD-3G, is it possible to upgrade to PRD-6G?

Yes, as long as you have a valid Compile-time License Key, you can upgrade from SATA-II to SATA-III. We will apply the payment for PRD-3G towards your payment of PRD-6G.

How can Zynq SSE be priced lower than what a typical SATA IP core costs?

The reason for pricing Zynq SSE is to reflect the needs of Zynq users who look for connectivity solutions, but not necessarily a full soft FPGA IP core as such:

In general, the advantage of an IP core is that you can instantiate it freely in your design. You can parameterize and change and instantiate the IP core in many ways and as many times as needed. If you purchased the RTL source code version, you could even change the functionality. The drawback is the cost (and time) of integrating an IP core and the effort you have to put into driver development. And, sometimes, there is a support burdon for the IP core vendor, too.

Zynq SSE is a turnkey reference design where the underlying IP core has been 'frozen'. You can instantiate it exactly once (and only once) per device. By integrating this with Linux - including Linux device drivers - and making this available for Zynq-only we are able to come up with a great price for a Single-Project-Use license.

We believe that this model has many advantages for all parties involved.

Can I use Zynq SSE without Linux?

No, Zynq SSE is technically and license-wise bundled with Zynq and Linux. However, we can support your project with a SATA IP core from ASICS.WS. Please read below and/or contact us.

Which Linux can I use?

We have extensively tested Zynq SSE for Xilinx PetaLinux 2013.04. You can download this from the following git repository:

In general, there is no reason why Zynq SSE should not work with other Linux Kernel versions applicable to Zynq.

What SATA performance will I see with Zynq SSE?

We took a conservative stand when we parameterized Zynq SSE. Key objective was to make it robust and work in almost all user cases. This limits the raw speed to approximately 200MB/sec for the PRD-3G. When we say 'raw speed' this is to and from the SATA Linux block device (a.k.a. /dev/sdX) without Linux filesystem layers involved. Obviously, filesystem handling adds to the processing burdon which leads to lower read/write speeds.

What if I need higher SATA performance than Zynq SSE offers?

If you need more performance than the raw speed to approximately 200MB/sec for the PRD-3, for example to max-out your super-fast SSD we believe we can help you. We are prepared to discuss with you acceleration options like bypassing the Linux system by writing directly into the SATA device, or other protocol acceleration techniques we have been working on. Just contact us directly!

Can I buy a SATA IP Core from MLE?

We would be more than happy to directly assist you in selecting and purchasing the right variant of a SATA IP Core from ASICS.WS. ASICS.WS has prepared us to discuss with you pricing and licensing options, or, for example, whether you should get HDL source code or just a netlist, or an evaluation, a single-project-use or a multi-project-use license.

And, obviously, we do know the ASICS.WS SATA Host Controller and DMA IP Core in-and-out. So you can ask us technical questions, too!

Can I buy a full turnkey system with hardware (PCB) and software from MLE?

Sure, we have done turnkey solutions in the past and will be happy to discuss details with you, including PCB design and manufacturing.

Do you provide more detailed information about the device utilization?

You can either download and compile the ERD for your target device and look at your Vivado utilization report. Or, below are the most important sections of the utilization report for a XC7Z100 device:

Slice Logic        
Site Type Used Loced Available Util%
Slice LUTs 5922 0 277400 2.13
  LUT as Logic 5794 0 277400 2.08
  LUT as Memory 128 0 108200 0.11
    LUT as Distributed RAM 10 0           
    LUT as Shift Register 118 0           
Slice Registers 4623 0 554800 0.83
  Register as Flip Flop 4623 0 554800 0.83
  Register as Latch 0 0 554800 0
F7 Muxes 35 0 138700 0.02
F8 Muxes 2 0 69350 <0.01
Site Type Used Loced Available Util%
Block RAM Tile 3 0 755 0.39
  RAMB36/FIFO* 3 0 755 0.39
    FIFO18E1 only 1           
    RAMB36E1 only 2           
  RAMB18 1 0 1510 0.06
    RAMB18E1 only 1           
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
Site Type   Used Loced Available Util%
BUFGCTRL  8 0 32 25
BUFIO     0 0 32 0
MMCME2_ADV 2 0 8 25
PLLE2_ADV 0 0 8 0
BUFMRCE   0 0 16 0
BUFHCE    0 0 168 0
BUFR      0 0 32 0

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