Systems Realization

Systems are more that the sum of their parts! And especially Embedded Systems are more than just hardware and software!

To build better Embedded Systems, faster, MLE utilizes state-of-the-art techniques for Systems Realization:

  • Transaction-Level Modeling – which is a powerful concept for architectural exploration and analysis at Electronic-System-Level (ESL). Based on the IEEE 1666 SystemC language standard subsystems implemented in VHDL or Verilog Hardware Description Language (HDL) – a.k.a. the Hardware – can be brought together with subsystems implemented in C or C++ – a.k.a. the Software.
  • Virtual Platforms (VP) such as QEMU from the Open Source ecosystem or the Virtual System Platform from Cadence Design Systems, Inc. which generate executable system models very early-on during the development phase when target hardware may not even be available.

Because these techniques offer important design visibility for the optimization, verification and debugging of complex Embedded Systems MLE will continue adopting new techniques for Systems Realization.