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Beyond the Bitstream:
MLE
FPGA Full System Stacks
Andreas Schuler
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● Andreas Schuler, B. Eng.
○ Director Applications, Missing Link Electronics
○ Product Owner, AMD Security and Partnership
● Core Expertise: Leading projects to success
○ Planning and Managing Projects
○ AMD Security Architectures
About the Speaker
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MLE – Experts for Domain-Specific Compute Architectures
Our Mission: From Software to Silicon!
● Deliver HW and SW for High-Performance
(Embedded) Compute Systems & Solutions
● Offering pre-validated subsystems with
FPGA IP blocks and open-source software
● Support customer projects with deep
expertise and hands-on design services
Headquartered in Silicon Valley with Design
Offices in Germany
● Founded 2010, employee owned
● 20+ Certified FPGA Designers
● Customers include technology leaders,
US and European government agencies,
Fortune 500 companies
● Partners to:
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MLE Design Services Expertise – FPGA as a Computer
● RTL and High-Level Synthesis using FPGA design flows
● AMD Zynq-7000 SoC in designs since Q1/2012
● AMD Zynq Ultrascale+ MPSoC in designs since Q4/2015
● AMD Zynq UltraScale+ RFSoC in designs since Q2/2018
● AMD Versal since Q1/2019
● PetaLinux / Vanilla Linux and Yocto-based SW development
● Multigigabit transceiver configurations
○ PCIe Gen2/3/4/5, SATA 3/6G, SAS 6/12G, NVMe, CXL
○ SDI-3/6/12G, JESD204B, DP/HDMI 4k, MIPI CSI-2 D-PHY
○ 10/25/40/50/100G Ethernet, Low Latency Ethernet
● Radar & Lidar for civil, mil/aero, automotive, industrial
● Image processing for HDMI, Displayport, SDI
● Time Sensitive Networking, Detnet, Layer-2/3 Switching
● Functional Safety Design Flows ISO 26262 (ASIL), IEC 61508 (SIL)
● Security & Trust (PUF, Crypto Accelerators , eFuses)
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Our Technology Achievements
● Patented technology in the fields of acceleration, mixed-signal, functional safety
○ US Patent 9,209,828 – Configurable Mixed-Signal Systems
○ US Patent 10,140,049 – Partitioning Systems Operation in Multiple Domains
○ US Patent 10,509,880 – Automation for Configurable Mixed-Signal Systems
○ US Patent 10,708,199 – Heterogeneous Packet-Based Transport
○ US Patent 10,848,442 – Secure Heterogeneous Packet-Based Transport
○ US Patent 11,356,388 – Real-Time Multi-Protocol Heterogeneous Packet-Based Transport
● 60+ Presentations at Technology Conferences and in Technology Journals
○ Embedded World Conferences
○ PCI-SIG Developers Conferences
○ Flash Memory Summits, SmartNICs Summit
○ FPGA Conferences
○ IBM Open Power Summit
○ Automotive Ethernet Congress
○ XILINX Developer Forum and Security Workshops
○ SNIA Storage Developers Conferences
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Architecture
1. Best approach for Performance?
2. What is available on the Market?
3. Design decisions which can be a burden later
in the Project
Full System Stacks:
- Architecture and design choices come
from +10 years of Design Service and IP
Development in the fields industrial,
medical, aerospace, automotive, test &
measurement.
- MLE is specialised for High Speed and
High Performance designs
Challenges of new Projects
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IP Integration
1. High IP Core costs
2. Understand the Configuration
3. Understand the Registers
4. Understand the Handling
5. Fine Tuning everything around the IP,
like Transceivers
6. IP Vendor may only care about his part
of the solution
Full System Stacks:
1. Single Unit Licensing creates low entry
costs
2. As IP creator we understand all
implications of the IP interfaces and
deliver an optimized configuration
3. We deliver a Full System Stack so we can
help in all aspects of of the design
Challenges of new Projects
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Drivers
1. Integrate and compile drivers
2. Integrate the needed packages
Full System Stacks:
1. Drivers and needed packages are
already integrated when delivered
Challenges of new Projects
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Applications
1. Write an application which handles the
driver well
Full System Stacks:
1. The package also includes an
Application Example which show the
initialisation, operation*:
read/write/connect/disconnect and
teardown
* Depends on the FPGA Full System Stack
Challenges of new Projects
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Hardware
1. Turnaround time of Hardware
development und later ramp up time.
Full System Stacks:
1. Hardware turnaround time reduced due
to SOM based approach: Spinning just
the carrier board is simpler and cheaper
then spinning the full board
2. Software Development can start
immediately with an eval carrier
3. For ramp up: Chip down design together
with SOM vendor can be much faster as
starting with a full PCB design as clock,
power, reset und many interfaces are
already available
Challenges of new Projects
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Example for Rapid Prototyping with Trenz Hardware
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Solution Category SoM (Carrier) Board IP/Driver Status
FFSS-TE0950-NPAP-10G Network - TE0950 NPAP-10G Launch
FFSS-TE0950-NPAP-25G Network - TE0950 NPAP-25G Launch
FFSS-TE0950-Netdev-10G Network - TE0950 Linux Netdev 10G Launch
FFSS-TE0950-Netdev-25G Network - TE0950 Linux Netdev 25G Launch
FFSS-TE0950-NVMePS Storage - TE0950 Linux nvme.h Available soon
FFSS-TE0950-NVMePL-x4 Storage - TE0950 NVMe Streamer x4 Available soon
FFSS-TE0950-NVMePL-x1 Storage TE0950 NVMe Streamer x1 Available soon
FFSS-TE0955-NPAP-10G Network TE0955 TEB0955 NPAP-10G Available soon
FFSS-TE0955-NPAP-25G Network TE0955 TEB0955 NPAP-25G Available soon
FFSS-TE0955-Netdev-10G Network TE0955 TEB0955 Linux Netdev 10G Available soon
FFSS-TE0955-Netdev-25G Network TE0955 TEB0955 Linux Netdev 25G Available soon
FFSS-TE0955-NVMePS Storage TE0955 TEB0955 Linux nvme.h Available soon
FFSS-TE0955-NVMePL-x4 Storage TE0955 TEB0955 NVMe Streamer x4 Available soon
FFSS-TE0955-NVMePL-x1 Storage TE0955 TEB0955 NVMe Streamer x1 Available soon
FFSS-ADA-VA330-NVMePLx4 Storage ADA-VA330 NVMe Streamer x4 Launch
FFSS-ADA-VA330-NVMePS Storage ADA-VA330 Linux nvme.h Launch
FFSS-ADA-V9202-NVMePLx4 Storage ADA-V9202 NVMe Streamer x4 Launch
FFSS-ADA-V9202-NVMePS Storage ADA-V9202 Linux nvme.h Launch
FFSS-ADA-VA210-NVMePLx4 Storage ADA-VA210 NVMe Streamer x4 Available soon
FFSS-ADA-VA210-NVMePS Storage ADA-VA210 Linux nvme.h Available soon
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Thank you
Any
questions?
