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In-Vehicle Network - Automotive

Zone Based Architecture with

Time Sensitive Network

Maximilian Sokol

(Andreas Braun / Andreas Schuler)

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● Friedrich Maximilian Sokol, M. Eng.

○ "Full-Stack" Digital Hardware Engineer, Missing Link Electronics

○ Driving high-performance solutions from initial system

architecture through to final hardware deployment.

● Core Expertise: Protocols on Silicon

○ Specialist in high-performance network stacks (TCP/IP) for

FPGAs.

○ Expertise spans system architecture, PCB design, and low-level

software.

About the Speaker

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MLE – Experts for Domain-Specific Compute Architectures

Our Mission: From Software to Silicon!

● Deliver HW and SW for High-Performance

(Embedded) Compute Systems & Solutions

● Offering pre-validated subsystems with

FPGA IP blocks and open-source software

● Support customer projects with deep

expertise and hands-on design services

Head-quartered in Silicon Valley with Design

Offices in Germany

● Founded 2010, employee owned

● 20+ Certified FPGA Designers

● Customers include technology leaders,

US and European government agencies,

Fortune 500 companies

● Partners to:

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MLE Design Services Expertise – FPGA as a Computer

● RTL and High-Level Synthesis using FPGA design flows

● AMD Zynq-7000 SoC in designs since Q1/2012

● AMD Zynq Ultrascale+ MPSoC in designs since Q4/2015

● AMD Zynq UltraScale+ RFSoC in designs since Q2/2018

● AMD Versal since Q1/2019

● PetaLinux / Vanilla Linux and Yocto-based SW development

● Multigigabit transceiver configurations

○ PCIe Gen2/3/4/5, SATA 3/6G, SAS 6/12G, NVMe, CXL

○ SDI-3/6/12G, JESD204B, DP/HDMI 4k, MIPI CSI-2 D-PHY

○ 10/25/40/50/100G Ethernet, Low Latency Ethernet

● Radar & Lidar for civil, mil/aero, automotive, industrial

● Image processing for HDMI, Displayport, SDI

● Time Sensitive Networking, Detnet, Layer-2/3 Switching

● Functional Safety Design Flows ISO 26262 (ASIL), IEC 61508 (SIL)

● Security & Trust (PUF, Crypto Accelerators , eFuses)

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Our Technology Achievements

● Patented technology in the fields of acceleration, mixed-signal, functional safety

○ US Patent 9,209,828 – Configurable Mixed-Signal Systems

○ US Patent 10,140,049 – Partitioning Systems Operation in Multiple Domains

○ US Patent 10,509,880 – Automation for Configurable Mixed-Signal Systems

○ US Patent 10,708,199 – Heterogeneous Packet-Based Transport

○ US Patent 10,848,442 – Secure Heterogeneous Packet-Based Transport

○ US Patent 11,356,388 – Real-Time Multi-Protocol Heterogeneous Packet-Based Transport

● 60+ Presentations at Technology Conferences and in Technology Journals

○ Embedded World Conferences

○ PCI-SIG Developers Conferences

○ Flash Memory Summits, SmartNICs Summit

○ FPGA Conferences

○ IBM Open Power Summit

○ Automotive Ethernet Congress

○ XILINX Developer Forum and Security Workshops

○ SNIA Storage Developers Conferences

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MLE Technology - Proudly Sourced Elsewhere

Example BMBF VERANO: Koherent digital Radar MLE optimizes CERN OHL White Rabbit to

AMD/Xilinx FPGAs

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Automotive Network History (1967)

1966 Oldsmobile Cutlass Convertible

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Today’s Expensive Wiring Nightmare

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Next: Zone-Based Architectures

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Next: Zone-Based Architectures

Example: Tesla's “Etherloop”¹

Model 3:

● Number of endpoints: 273

● Number of cables: 490

Cybertruck:

● Number of endpoints: 368

● Number of cables: 155

¹ https://insidetesla.de/tesla-cybertruck-innovatives-etherloop-system/

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Why Zone Based Architecture? Signal 2 Data

Example: Camera

Camera

Zone

Controller

GSML/MIPI

Car Server

Image

Frame/Lane

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Why Zone Based Architecture? Signal 2 Data

Example: Camera

Camera

Zone

Controller

GSML/MIPI

Car Server

Image

Frame/Lane

Zone can provide preprocessed

data:

- Rescaled

- ROI

- etc.

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture

Camera

Zone

Controller

GSML

/MIPI

Publish:

Camera Data

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture

Camera

Zone

Controller

GSML

/MIPI

Camera

Stream

Publish:

Camera Data

Car Server

Subscribe:

Camera Data

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture

Camera

Zone

Controller

GSML

/MIPI

Camera

Stream

Publish:

Camera Data

Car Server

Subscribe:

Camera Data

Publish:

Req. Speed

Process

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture

Camera

Zone

Controller

GSML

/MIPI

Camera

Stream

Publish:

Camera Data

Zone

Controller

Subscribe:

Req. Speed

Throttle

Control

Car Server

Subscribe:

Camera Data

Publish:

Req. Speed

Process

Req.

Speed

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture

Camera

Zone

Controller

GSML

/MIPI

Camera

Stream

Publish:

Camera Data

Zone

Controller

Subscribe:

Req. Speed

Throttle

Control

Signal 2 Data

Car Server

Subscribe:

Camera Data

Publish:

Req. Speed

Process

Req.

Speed

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture

Camera

Zone

Controller

GSML

/MIPI

Camera

Stream

Publish:

Camera Data

Zone

Controller

Subscribe:

Req. Speed

Req.

Speed

Throttle

Control

Provider

Consumer

Car Server

Subscribe:

Camera Data

Publish:

Req. Speed

Process

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture: Different example

Front Zone

Controller

Pub: Tap

Indicator

Pub: Press

Indicator

Indi-

cator

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture: Different example

Front Zone

Controller

Car Server

Pub: Tap

Indicator

Pub: Press

Indicator

Back Zone

Controller

Sub: Tap

Indicator

Sub: Press

Indicator

Indi-

cator

Turn

Signal

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture: Different example

Front Zone

Controller

Car Server

Pub: Tap

Indicator

Pub: Press

Indicator

Back Zone

Controller

Sub: Tap

Indicator

Sub: Press

Indicator

Sub: Tap

Indicator

Sub: Press

Indicator

Indi-

cator

Turn

Signal

Turn

Signal

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture: Different example

Front Zone

Controller

Car Server

Pub: Tap

Indicator

Pub: Press

Indicator

Back Zone

Controller

Sub: Tap

Indicator

Sub: Press

Indicator

Sub: Tap

Indicator

Sub: Press

Indicator

Indi-

cator

Turn

Signal

Turn

Signal

Coordinator / Broker

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Why Zone Based Architecture? Signal 2 Data

Middleware: pub / sub architecture: Different example

Front Zone

Controller

Car Server

Pub: Tap

Indicator

Pub: Press

Indicator

Back Zone

Controller

Sub: Tap

Indicator

Sub: Press

Indicator

Sub: Tap

Indicator

Sub: Press

Indicator

Indi-

cator

Turn

Signal

Turn

Signal

Middleware

Coordinator / Broker

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Why Zone Based Architecture? Signal 2 Data

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A Big Technological Challenge

High Bandwidth

Reliable

Low-Latency

Time-Deterministic

Networking

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Evolution of Automotive Networks

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Auto/TSN for Zone Architectures / in-vehicle network

Automotive data over Time-Sensitive Networks, based on open IEEE standards

● Virtualizes in-vehicle network infrastructure

● Full “legacy” connectivity plus enabling “new” high data rate interfaces (PCIe, GMSL, MIPI CSI2)

● Delivers bandwidth, scalability, security, Functional Safety

CAN

LIN

Ethernet

CAN

LIN

Ethernet

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

High Bandwidth

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

High Bandwidth

Low-Latency

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

High Bandwidth

Low-Latency

Time-Deterministic

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

High Bandwidth

Low-Latency

Time-Deterministic

Reliable

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

High Bandwidth

Low-Latency

Time-Deterministic

How do we make this reliable?

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Auto/TSN for Zone Architectures / in-vehicle network

CAN

LIN

10BASE-T1S

CAN

LIN

10BASE-T1S

Auto/TSN over

10G/25G/50G

Ethernet

Packetizer

De-

Packetizer

PCIe

MIPI CSI-2

PCIe

MIPI CSI-2

High Bandwidth

Low-Latency

Time-Deterministic

How do we make this reliable?

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Building a High Bandwidth, Reliable TSN

CAN

LIN

10BASE-T1S

Packetizer, fully in FPGA, no Software involved!

PCIe

MIPI CSI-2

PCI-E to AXI

Bridge

MLE NPAP

(TCP / IP)

Ethernet

Mac

MLE

Auto/TSN

● Tunnel any Protocol reliably over a Network

● Using proven protocols, fully implemented in Hardware

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NPAP

AXI4-Stream

MAC

● Network Protocol Accelerator Platform

● TCP / UDP / IP Stack Fully in Hardware

+

MLE Network Protocol Accelerator Platform (NPAP)

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Software TCP/IP

Stack

TCP/IP Offload

Engine (TOE)

MLE NPAP

Hardware-based

TCP/IP Stack

MLE NPAP Hardware-

based Customized

TCP/IP Stack

Comparison of software

and hardware-based

TCP/IP stacks

Why NPAP? No Software Involved!

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FPGA

Why NPAP? No Software Involved!

ETH

IP

stack_ctrl

UDP

TCP

MLE NPAP

10/25/50 GigE PCS/PMA

Ethernet

IPv4

TCP

UDP

ICMP

IGMP

TCP1 TCP2

10/25/50 GigE MAC

Network Side

User Side

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Why NPAP? Well Tested!

Evaluation

Reference

Design

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Why NPAP? Well Tested!

Evaluation

Reference

Design

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Why NPAP? Well Tested!

Evaluation

Reference

Design

42

Why NPAP? Well Tested!

Evaluation

Reference

Design

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Why NPAP? Well Tested!

Evaluation

Reference

Design

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Why NPAP? Well Tested!

Evaluation

Reference

Design

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Generic Source Code running on

● AMD

○ Virtex 4 to Virtex UltraScale+

○ Kintex to Kintex UltraScale+

○ Artix UltraScale+

○ Zynq-7000

○ Zynq UltraScale+ MPSoC

○ Zynq UltraScale+ RFSoC

○ Versal ACAP Series

● Altera

○ Cyclone IV series

○ Cyclone 10 GX series

○ Stratix V

○ Stratix 10 GX series

○ Agilex 5 D, E Series

○ Agilex 7 F, I, M Series

Why NPAP? Well Tested!

● Microchip

○ Polarfire and PolarFire SoC

● Lattice

○ Avant-G

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Why NPAP? Well Tested!

Impairment Generator

● Designed to emulate packet-level

impairments in real-time.

● Injects emulated errors into MAC

AXI4-Stream datapaths

● Ideal for verifying the resilience and

error-handling capabilities of

downstream components

NPAP

MAC / PHY

Impairment

Generator

Impairment

Generator

TX

RX (impaired)

TX (impaired) RX

User side

Network side

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Why NPAP? Well Tested!

Diagnostics

● Lots of counters accessible via register space, e.g.:

○ TX / RX Segments

○ TX Retransmissions

CAN

LIN

10BASE-T1S

PCIe

MIPI CSI-2

PCI-E to

AXI

Bridge

MLE

NPAP

(TCP / IP)

Ethernet

Mac

MLE

Auto/TSN

Diagnose network issues

Optimize parameters for network

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Why NPAP? Optimization!

● Reduce unnecessary Latency:

○ Decrease Retransmission

Timeout (RTO)

○ Check TX Retransmissions

○ Repeat until TX

Retransmissions rise

NPAP TCP Stack

Segment

Ack

X

Retransmission

RTO too long

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Why NPAP? Optimization!

● Reduce unnecessary Latency:

○ Decrease Retransmission

Timeout (RTO)

○ Check TX Retransmissions

○ Repeat until TX

Retransmissions rise

NPAP TCP Stack

Segment

Ack

Retransmission

RTO too short

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Why NPAP? Optimization!

● Reduce unnecessary Latency:

○ Decrease Retransmission

Timeout (RTO)

○ Check TX Retransmissions

○ Repeat until TX

Retransmissions rise

NPAP TCP Stack

Segment

Ack

X

Retransmission

RTO just right

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Tackling Technical Challenges: Accelerate FPGA

Design

Shift-Left with Trenz,

Starter-Kit to SoM

Rapid Prototyping in

FPGAs

TE0955

Software

development

Use off-the-shelf

SoM

+

Design

Carrier Board

+

Together with Trenz Electronic we

provide Rapid FPGA Prototyping

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MLE Auto/RPS

Application is for SDV / Zonal Architectures:

● Data-centricity shifts SW development

focus from signal to data

● API-first to de-couple and abstract

based on vehicle data model

● Modularity & autonomy to enable

flexible, scalable SW with high re-use

⇒ Focus on Software Engineers

⇒ Full FPGA System Stack, Ready-to-Run

⇒ FPGA is fully transparent (don’t have to

touch, unless you want to)

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MLE Auto/RPS

Auto/RPS supports connectivity for (almost) all relevant I/O interfaces:

● 1 Gig Ethernet (for example for remote access and housekeeping)

● USB 2.0 for JTAG and console (supports even keyboard and

mouse)

● 2x ports for 25G Ethernet (up to 4 ports optional)

● MIPI CSI-2 x2 Camera Input (optional)

● Up to 2x CAN-FD (via CRUVI HS) (optional)

● Up to 2x CAN 2.0B (via CRUVI HS) (optional)

● NVMe M.2 SSD (optional via Opsero FMC M.2 adapter)

● PCIe 4.0 x4 via 4x GTYP (optional, for high-speed debugging etc)

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MLE Auto/RPS

Auto/RPS supports connectivity for (almost) all relevant I/O interfaces:

● 1 Gig Ethernet (for example for remote access and housekeeping)

● USB 2.0 for JTAG and console (supports even keyboard and

mouse)

● 2x ports for 25G Ethernet (up to 4 ports optional)

● MIPI CSI-2 x2 Camera Input (optional)

● Up to 2x CAN-FD (via CRUVI HS) (optional)

● Up to 2x CAN 2.0B (via CRUVI HS) (optional)

● NVMe M.2 SSD (optional via Opsero FMC M.2 adapter)

● PCIe 4.0 x4 via 4x GTYP (optional, for high-speed debugging etc)

Working on a V2 together with

Trenz to support even more I/O

interfaces

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Auto/TSN for Zone Architectures / in-vehicle network

● AMD Versal VM1802 for

“emulating” ADAS compute

and connectivity

● AMD Versal VE2303 for

“emulating” Zone ECUs /

gateways

Budget: 88 Mio EUR

Key Objectives:

● Zone-base architecture

● Auto SoC / Chiplets

● Mechanical / thermal

BMBF CeCaS

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MLE Auto/RPS in Action

as Zone Controller

Auto/RPS

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Auto/RPS in Action

Presented at BOSCH Automotive Ethernet Conference, Oct 2024, Renningen

Central Car Server (CeCaS)

CeCaS CCU

Auto/RPSAuto/RPS

AMD VM1802

AMD VE2302

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Conclusion

However:

1. Zonal architectures require fast networks and rapid development.

2. We provide the technology: Reliable Networking using ultra-fast TSN.

3. We provide the methodology: Auto/RPS for rapid FPGA prototyping.

Turning today's automotive wiring

mess into tomorrow's automotive

architecture is doable by using a

Zone Based Architecture.

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Thank you

Any

questions?

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Contact:

Maximilian Sokol

max.sokol@missinglinkelectronics.com

Andreas Schuler

Andreas.schuler@missinglinkelectronics.com

Missing Link Electronics

Industriestraße 10

89231 Neu-Ulm

www.missinglinkelectronics.com