Heterogeneous Multi-Processing for SW-
Defined Multi-Tiered Storage Architectures
Endric Schubert (MLE)
Ulrich Langenbach (MLE)
Michaela Blott (Xilinx Research)
SDC, 2017
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Heterogeneous Multi-Processing for
Software-Defined Multi-Tiered Storage Architectures
Who – Xilinx Research and Missing Link Electronics
Why – Multi-tiered storage needs predictable performance scalability,
deterministic low-latency and cost-efficient flexibility / programmability
What – Tera-OPS processing performance in a single-chip heterogeneous
compute solution running Linux
How – Combine “unconventional” dataflow architectures for acceleration &
offloading with Dynamic Partial Reconfiguration and High-Level Synthesis
Content
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Xilinx Research and Missing Link Electronics
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Xilinx – The All Programmable Company
$2.38B FY15 revenue
>55% market segment share
3,500+ employees worldwide
20,000 customers worldwide
3,500+ patents
60 industry firsts
XILINX - Founded 1984
Headquarters
Research and Development
Sales and Support
Manufacturing
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Xilinx Research - Ireland
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Applications & Architectures
Through application-driven
technology development with
customers, partners, and
engineering & marketing
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Vision: The convergence of software and off-the-shelf programmable logic
opens-up more economic system realizations with predictable scalability!
Mission: To de-risk the adoption of heterogeneous compute technology by
providing pre-validated IP and expert design services.
Certified Xilinx Alliance Partner since 2011, Preferred Xilinx PetaLinux Design
Service Partner since 2013.
Missing Link Electronics
Xilinx Ecosystem Partner
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Missing Link Electronics Products & Services
TCP/IP & UDP/IP Network
Protocol Accelerators at
10/25/50 GigE line-rate.
Patented Mixed Signal
systems solutions with
integrated Delta-Sigma
converters in FPGA logic.
SATA Storage Extension for Xilinx
Zynq All-Programmable
Systems-on-Chip.
A team of FPGA and Linux
engineers to support our
customer’s technology projects
in the USA and Europe.
Key-Value-Store Accelerator for
hybrid SSD/HDD memcached
and object storage.
Low-Latency Ethernet MAC form
German Fraunhofer HHI.
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Motivation
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Software significantly impacts
latency and energy efficiency
in systems with nonvolatile
memory
However, software-defined
flexibility is necessary to fully
utilize novel storage
technologies
Hyper-capacity hyper-
converged storage systems
need more performance, but
within cost and energy
envelopes
Technology Forces in Storage
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Source: Steven Swanson and Adrian M. Caulfield, UCSD
IEEE Computer, August 2013
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CPU system performance scalability is limited
The Von Neumann Bottleneck [J. Backus, 1977]
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New Compute Architectures are needed
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CPU system performance scalability is limited
Spatial computing offers further scaling opportunity
Spatial vs. Temporal Computing
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New Compute Architectures are needed to
take advantage of this
Sequential Processing
with CPU
Parallel Processing
with Logic Gates
Source: Dr. Andre DeHon, Upenn: “Spatial vs. Temporal Computing”
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Architectural Choices for Storage Devices
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Log P E R F O R M A N C E
Log F L E X I B I L I T Y
Log P O W E R D I S S I P A T I O N
10
3
. . . 10
4
10
5
. . . 10
6
Application
Specific Signal
Processors
Digital
Signal
Processors
General
Purpose
Processors
Application
Specific
ICs
Physically
Optimized
ICs
StrongARM110
0.4 MIPS/mW
TMS320C54x
3MIPS/mW
ICORE
20-35 MOPS/mW
Source: T.Noll, RWTH Aachen
Field
Programmable
Devices
Tera OPS
Processing Power
At low Wattage
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Use Case: Image/ Video Storage
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A Flexible All Programmable Storage Node
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Storage Node
MPSoC FPGA
Reconfigurable
Processing
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
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Storage Node
Meta Data Extraction, e.g. Image Quality Metrics
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Meta Data Extraction
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
• Partially under and over exposed
• Medium contrast
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Storage Node
Processing, e.g. Thumbnailing, Auto-Correction
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Thumbnailing
Auto Correction
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
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Storage Node
Semantic Feature Extraction, e.g. Classification
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Semantic Feature
Extraction
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
• Group of People
• Xilinx
• Outdoor
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Storage Node
Semantic Search Support
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Semantic Feature Search
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
• Group of People
• Xilinx
• Outdoor Scene
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Storage Node
Performance Metrics, e.g. Bandwidth, Latency
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Semantic Feature Search
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
• Performance Counter
• Pattern Matching
• ID Generation for Tracing
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Runtime Programmability
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Storage Node
Reconfigurable
Processing
Network
NVMe
Drive
NVMe
Drive
NVMe
Drive
Monitoring
Meta Data
Extraction
Semantic
Feature
Extraction
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Architectural Concepts
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Heterogeneous compute device as a single-chip solution
Direct network interface with full accelerator for protocols
Performance scaling with dataflow architectures
Scaling capacity and cost with a Hybrid Storage subsystem
Software-defined services
Key Concepts Presented at SDC-2016
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SDC-2016: Single-Chip Solution for Storage
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DDRx
channels
DDRx
channels
M.2 NVMe
drives
M.2 NVMe
drives
M.2 NVMe
drives
M.2 NVMe
drives
DDRx
channels
DDRx
channels
DDRx
channels
Data Node
FPGA fabric (PL)
Processing System with quad core 64b processors (A53)
TCP/IP stack
Petalinux
Memory
management
Key Value Store
Abstraction
(memcached)
NVMe
interface
Memory
controller
Hybrid
Memory
System
Network
management
Router
Xilinx IP
SD Services
MLE IP
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SDC-2016: Hardware Accelerated Network Stack
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DDRx
channels
DDRx
channels
M.2 NVMe
drives
M.2 NVMe
drives
M.2 NVMe
drives
M.2 NVMe
drives
DDRx
channels
DDRx
channels
DDRx
channels
Data Node
FPGA fabric (PL)
Processing System with quad core 64b processors (A53)
TCP/IP stack
Petalinux
Memory
management
Key Value Store
Abstraction
(memcached)
NVMe
interface
Memory
controller
Hybrid
Memory
System
Network
management
Router
TCP/IP Full Accelerator
Supports 10/25/50
GigE line-rates
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Now: 10 Gbps demonstrated with a 64b data path @ 156MHz using 20% of FPGA
Next: 100 Gbps can be achieved by using a 512b @ 200MHz pipeline for example
SDC-2016: Dataflow architectures for
performance scaling
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Streaming Architecture:
Flow-controlled series of processing
stages which manipulate and pass
through packets and their associated
state
Source: Blott et al: Achieving 10Gbps line-rate key-value stores with FPGAs; HotCloud 2013
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SSDs combined with DDRx channels can be used to build high
capacity & high performance object stores
Concepts and early prototype to scale to 40TB & 80Gbps key
value stores
SDC-2016: Scaling Capacity via hybrids
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Parser
Hash
Lookup
Value
Store
Access
Formatter
DDRx
channels
DDRx
channels
M.2 NVMe
drives
M.2 NVMe
drives
M.2 NVMe
drives
M.2 NVMe
drives
DDRx
Hash Table
DDRx
Channels
Hash Table
Value
Store
Value
Store
Hybrid MemorySystem
Source: HotStorage 2015, Scaling out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory
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SDC-2016: Handling High Latency Accesses
without Sacrificing Throughput
Read SSDRead SSD
Read SSD
100usec
• Dataflow architectures: no limit to number of outstanding requests
• Flash can be serviced at maximum speed
Read SSDRead SSD
Read SSD
time
Read SSD
Read SSD
Read SSDRead SSD
Read SSD
Request
Buffer
Read SSD
Read SSD
Read SSDRead SSD
Read SSD
ResponseResponseResponse
ResponseResponseResponse
ResponseResponse
Response
ResponseResponseResponse
ResponseResponse
Response
Cmd:
Rsp:
Read SSDRead SSD
Read SSD
Read SSD
Read SSD
Read SSDRead SSD
Read SSD
Read SSD
Read SSD
Read SSDRead SSD
Read SSD
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Software-Defined Services
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Spatial computing of additional services at no performance cost until
resource limitations are reached
Software-Defined ServicesSoftware-Defined Services
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Software-Defined Services
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Offload engines for Linux Kernel Crypto-API
Non-intrusive latency analysis via PCIe TLP “Tracers”
Inline processing with Deep Convolutional Neural Networks
Declarative Linux Kernel Support Partial Reconfiguration
Software-Defined Services – Proof-of-Concepts
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Crypto-API is a cryptography framework in the Linux kernel used
for encryption, decryption, compression, de-compression, etc.
Needs acceleration to support processing at higher line-rates
(100 GigE).
Open Source software implementation that follows a streaming
dataflow processing architecture
– Hardware Interface: AXI Streaming
– Software/ Hardware Interface: SG-DMA in, SG-DMA out
High-Level Synthesis generated accelerator blocks from
reference C code
Software-Defined Services - Example 1)
Accelerating the Linux Kernel Crypto-API
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System Architecture of Crypto-API Accelerator
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Performance analysis and ongoing monitoring of bandwidth and
latency in distributed systems is difficult.
– Round-trip times
– Time-outs
– Throttling
When done in software, results get distorted by additional
compute burden.
When done in Programmable Logic, it can be (clock cycle)
accurate and non-intrusive via adding so-called “Tracers” into
the dataflow.
Software-Defined Services - Example 2)
Non-Intrusive Latency Analysis via PCIe TLP Tracers
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Tracers within PCIe Transaction Layer Packets (TLP)
– Based on addresses/ IDs, detected at PCIe switches and endpoints
– Transparent for transport layer (Ethernet, etc)
Tracer-Based Performance Analysis
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Full implementation on network with multiple boards
Proof-of-Concept Implementation
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Latency Monitoring WithTracers - Overview
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Latency Monitoring with Tracers - Results
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Deep Convolutional Neural Networks (CNN) have demonstrated
values in classification, recognition and data-mining.
However, CNN can be very compute intensive, when done at
single or double float precision.
Recent approaches involve reduced precision (INT8, or even
less), as well as dataflow-oriented compute architectures.
– Taps into tremendous compute power within Programmable Logic
What if, CNN can be run close to the data, within the storage
node?
Software-Defined Services - Example 3)
Inline Processing w/ Neural Networks
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Streaming Dataflow Processing in BNN Inference
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Courtesy “FINN: A Framework for Fast, Scalable Binarized Neural Network Inference”,
Umuroglu, Fraser, Blott et al., 25
th
Symp. on FPGA, 2017
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BNN Results
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Courtesy “FINN: A Framework for Fast, Scalable Binarized Neural Network Inference”,
Umuroglu, Fraser, Blott et al., 25
th
Symp. on FPGA, 2017
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Supports both full and partial reconfiguration of FPGAs
Adds a device tree interface for controlling the partial
reconfiguration process
Handles all FPGA internal processes
Abstract device and vendor neutral interface
Software-Defined Services – Infrastructure
Linux Kernel FPGA Framework
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Linux FPGA Framework Architecture
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A Declarative Partial Reconfiguration Framework
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Platform: ZC706
Bitstream Size: 5.9 MiB
Overall latency: ≈135 ms
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Conclusion & Outlook
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Trend towards unconventional architectures
– A diversification of increasingly heterogeneous devices and systems
– Convergence of networking, compute and storage within single
nodes
– CPU-only processing runs out of steam
Key concepts for demonstrating Software-Defined Services
– Offload engines for Linux Kernel Crypto-API
– Non-intrusive latency analysis via PCIe TLP “Tracers”
– Inline processing with Deep Convolutional Neural Networks
Results:
– On commercially available hardware
– Available for collaboration or in-house development
Conclusion
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Xilinx Zynq UltraScale+ MPSoC (XCZU19EG)
– ARM Cortex A-53 quad-core, ARM Coretx R5 dual-core, 1,968 DSP slices
– 1.1 million system logic cells, 34Mbit BRAM, 36Mbit UltraRAM
– 5x PCIe Gen3/4, 4x 100GigE, 44x 16.3Gbps, 28x 32.72Gbps
Single-Chip Implementation
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Sidewinder-100 from Fidus Systems
Accelerator IP and Linux BSP from MLE
Commercially Available Development System
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Dual m.2 SSDs
Dual
DDR4LP
SODIMM
NGFF
8643
Dual
QSFP28
PCIe Gen4 x8
PCIe Gen3 x8
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Backup
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Binarized Neural Networks (BNN):
Training with float, CNN Inference runs at reduced precision
– Less data (Mbytes) for parameters, less compute burdon.
Reduced Precision Neural Networks
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Design automation runs scheduling and resource binding to generate
RTL code comprising data paths plus state machines for control flow
Working Principles of High-Level Synthesis
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Automated performance
optimizations via parallelization
at dataflow level
Benefits of HLS-Based C/C++ FPGA Design
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Automatic interface synthesis
and driver code generation for
HW/SW connectivity
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Reconfiguration Performance
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Configuration Latency
Deconfiguration Latency
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Scheduling Latency - Profiling Results
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Measurement of example system (AES accelerator on ZC706 board)
Measured latencies via ftrace function entry and exit timestamps
Bitstream Size: 5.9 MiB
Overall latency: ≈135 ms
20%
63%
16%
1%
Runtime [%]
Load Bitstream
Partial Reconfiguration
Load Platform Driver
Rest incl. Framework
