Our Mission: If It Is Packets, We Make It Go Faster – today more on PCIe, this time, Powering PCIe Cards with FPGAs…
And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet; PCI Express (PCIe), CXL, OpenCAPI; data storage using SATA, SAS, USB, NVMe; video image processing using HDMI, DisplayPort, SDI, FPD-III.
To move packets you need power, but how much can you draw from an interface?
PCI Express Cards Consumption Limit
PCIe has been around for a long time, since 2003, and many people know the maximum power draw of 75W per PCIe slot, but is it that simple? The short answer is no, but let’s have a look into the spec. It states that all cards can consume up to 3A on the 3.3 V power rail with the following restrictions applying:
- x1 cards: 0,5A on 12V, but overall consumption limit is 10W
- x4 – x16 cards: 2,1A on 12V, but overall consumption limit is 25W
But where does the 75W come from? Well, exceptions apply:
High power devices can draw more power after the initialization and configuration:
- x1 cards can consume 25W
- x16 cards can consume 75W
Using Additional Connectors for Higher PCIe Card Consumption
With additional connectors (6pin and 8 pin) cards can consume up to 300W. A 6 pin adds 75W while a 8 pin adds 150W.
But be careful, in the FPGA world there are two versions of the 6/8 pin Molex Mini-Fit Jr connectors, the Xilinx and the PCIe option.
The 6 Pin option has 2 pins (3 and 4) swapped. If you mix up the connectors 12V will directly connect to Ground, this can destroy your device.
|6 Pin Power Connector|
|Pin||PCIe Spec||AMD/Xilinx Dev Boards|
|1||+12 V||+12 V|
|2||+12 V||+12 V|
The 8 Pin option the changes are less subtle, all pins have a different function and cause an electrical short.
|8 Pin Power Connector|
|Pin||PCIe Spec||AMD/Xilinx Alveo Cards|