Category Archives: Datasheet

Overview

MLE NPAP Datasheet Overview MLE NPAP is a complete subsystem of a high-performance RTL based, standalone network stack featuring transparent handling of complete TCP/IPv4 and UDP/IPv4 protocol tasks, including packet encoding, packet decoding, acknowledge generation, link supervision, timeout detection, retransmissions and fault recovery.  MLE NPAP supports complete automatic connection control including tear up and tear down. Compute and manage retransmission timers as in RFC 6298. Transparent checksum generation and checksum checking, integrated flow control. RFC 9293 compatibility (TCP/IPv4 stack for Windows and Linux).  MLE NPAP has been optimized to ensure the best bandwidth-delay product performance for your application. To guarantee delivery of full performance and reliability Team MLE will support you in all engineering aspects: System-level architecture design where aspects such as mapping ingress / egress data streams to TCP sessions, or handling TCP’s congestion control, or optimizing the bandwidth-delay-product are handled in order to meet system-level bandwidth and latency requirements.  Chip-design and integration i.e. managing ASIC/FPGA resources, interfacing with the network PHYs and/or Multi-Gigabit Transceivers (MGT), handling on-chip streaming (such as AXI beats) while integrating MLE NPAP into your FPGA or ASIC device on your target hardware. Network administration which includes configuring TCP/UDP servers and clients as well as planning and administering the MAC and IPv4 addresses within each system as

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Key Features

MLE NPAP Key Features With a focus on reliability and low, deterministic latency, MLE NPAP is a very resource-efficient network protocol accelerator platform for integration into ASIC and FPGA: Interface to 1 / 2.5 / 5 / 10 / 25 / 40 / 50 / 100 / 200 / 400 Gigabit Ethernet Full-duplex with 128 bit-wide bidirectional datapaths Full line rate of 100 Gbps, or faster, per instance in ASIC Full line rate of 70 Gbps, or faster, per instance in FPGA (depending on FPGA device) Low and deterministic one-way latency (typ. 500 nanoseconds) with full TCP/UDP/IPv4 compliance Network diagnostics functions (optional) Network Impairment Generators (optional) TCP session priority management (optional) Transport Layer Security (TLS) (optional) Time-Sensitive Networking (TSN) (optional) Precision Time-Synchronization IEEE 1588-HA (optional) Designed for maximum flexibility, NPAP implements in RTL logic all the relevant network communication protocols: IPv4 The core of the most standards-based networking protocols TCP Reliable connectivity for direct secured connectivity UDP Widespread protocol to enable simple direct or multicast communication RRRRP Reliable, Rapid Request-Response Protocol based on Stanford HOMA ICMPv4 Diagnostic protocol to validate connections IGMPv4 Enables joining of multicast groups (optional) Due to its modularity and parameterizability, MLE NPAP can easily be enhanced with other proprietary and/or application specific protocols. With a focus on ASIC

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Technical Specifications

MLE NPAP Technical Specifications FeatureSpecificationSupported on-chip Interfaces128 bit wide AXI4-StreamCompatibility with 3rd party Ethernet PHY interfacesStandard IEEE Ethernet PHYs with RMII, GMII, XGMII, etc via PCS/PMA via ASIC/FPGA Ethernet SubsystemCompatibility with 3rd party Ethernet Media Access ControllersFraunhofer HHI 10G/25G Low-Latency MACAMD/Xilinx 10G/25G Ethernet Subsystem (PG210)AMD/Xilinx 100G Ethernet Subsystem (PG165, PG203, PG314)Altera 10G / 25G Ethernet FPGA IPMicrochip PolarFire FPGA 10G Ethernet (UG0727)Lattice 10G / 25G Ethernet IP (FPGA-IPUG-02245)Supported protocols (Hardware based)Ethernet, ARP, IPv4, ICMPv4 (response only), IGMPv4, UDP & TCP, DHCP (client only)Number of simultaneous connectionsOne per TCP Core instantiation – see “Architecture Choices” below, a TCP Core in NPAP relates to a TCP socket in LinuxMessage SizesSupport for Ethernet Jumbo Frames of arbitrary lengthInterface to applicationDatapath via AXI4-Stream 128-bitand separate custom TCP command interfaceSupported FPGAs  Complete stack uses generic VHDL code (IEEE-1076 2002 or 2008, depending on NPAP version)AMD/Xilinx Virtex 4 to Virtex UltraScale+AMD/Xilinx Kintex to Kintex UltraScale+AMD/Xilinx Artix UltraScale+AMD/Xilinx Zynq-7000AMD/Xilinx Zynq UltraScale+ MPSoCAMD/Xilinx Zynq UltraScale+ RFSoCAMD/Xilinx Versal ACAP SeriesAMD Versal Gen2Altera Cyclone IV seriesAltera Cyclone 10 GX seriesAltera Stratix VAltera Stratix 10 GX seriesAltera Agilex 5 D, E SeriesAltera Agilex 7 F, I, M SeriesLattice Avant-G, Avant-XMicrochip Polarfire and PolarFire SoCPerformance70 Gbps line rate, or faster, for single TCP/IPv4 session (depending on clock rate, see below)Typ. 500 ns transport delay

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Latency Analysis Results

MLE NPAP Latency Analysis Results MLE analyzed processing latency using RTL simulation of two instances of MLE NPAP (using different clock speeds) connected via 10G LL MAC via XGMII (clocked at 156.25 MHz). TCP Payload Size [Byte]Clock cyclesLatency [ns] at 175 MHzLatency [ns] at 322 MHzLatency [ns] at 550 MHz162354.3192.5112.73267382.9208.1121.86473417.1226.7132.716091520.0282.6165.5448145828.6450.3263.69602411,377.1748.4438.212162891,651.4897.5525.514563341,908.61,037.3607.3 Latency was measured “one-way, door-to-door”: Using RTL simulation we count the number of clock cycles it takes from sending payload data from one MLE NPAP instance (TX) via the full MLE NPAP kernel until the other instance of MLE NPAP instance receives that payload data (RX). Here the system-level block diagram: Obviously, increasing the NPAP clock frequency will reduce latency for asynchronous NPAP subsystems. More information on dependable latency numbers can be found in our Technical Brief “Myth-Busting Latency Numbers for TCP Offload Engines.” Myth-Busting Latency Numbers for TCP Offload Engines Next: NPAP IP-Core Deliverables

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IP-Core Deliverables

MLE NPAP IP-Core Deliverables MLE NPAP deliverables include IEEE 1685 IP-XACT packages which include NPAP Kernel plus NPAP Support IP blocks plus non-IP-XACT FPGA reference design projects. The following design blocks are part of a typical delivery package: Low-Latency Ethernet MAC for 10G/25G NPAP Kernel with IPv4, TCP, UDP NPAP Support IP Data Generator Checker(great for system-level testing and for performance tuning) TCP Command Application TCP Demo Application UDP Demo Application Netperf Control Application Hardware Abstraction Layer (HAL) python package Network Statistics and Diagnostics (optional) Network Impairment and Bit Error Insertion (optional) Evaluation Reference Design (as FPGA Design Project Archive) Next: NPAP Developer Documentation

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Developer Documentation

MLE NPAP Developer Documentation A comprehensive product design guide of MLE NPAP and a detailed description of the support IPs and their documentation is available under license: NPAP Product Guide for the KernelDocuments the features, limitations, the configuration parameters and the interfaces of the NPAP Kernel. NPAP Product Guide for the LL-MACDocuments the features, configuration parameter and interfaces for the MLE MAC IP Core running at 10GBit/s or 25Gbit/s line rates NPAP Product Guides for the TCP App TCP Command ApplicationDocuments attributes, ports and AXI4-lite registers of the IP Core responsible for configuring a TCP session in the NPAP Kernel. TCP Demo ApplicationDocuments attributes, ports and AXI4-lite registers of the IP Core responsible for handling the data flow of a TCP session. NPAP Product Guide for the UDP Demo ApplicationDocuments attributes, ports and AXI4-lite registers of the IP Core handling an UDP session. NPAP  Product Guide for the Netperf Control ApplicationDocumentation is currently work in progress NPAP  Product Guide for the Data Generator / Checker (DGC)Documents everything necessary to include, configure or interact with the data generator and checker in your design. NPAP Product Guide for the Impairment Generator ApplicationDocuments attributes, ports and AXI4-lite registers of the IP core, which can introduce a variable bit-error rate. NPAP User Guide for the Hardware

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Benchmarking using Netperf

MLE NPAP Benchmarking using Netperf MLE NPAP can instantiate a fully accelerated version of Netperf and many of our Evaluation Reference Designs are parameterized to integrate this. This Netperf/Netserver block is compatible with open source Netperf 2.6 and can be used for system-wide tuning, for functionality analysis and for performance benchmarking. The charts below show the results of a 25 GbE NPAP-to-NPAP benchmark, underlining NPAP’s superior performance: Consistent High Throughput: The first chart, measuring a TCP_STREAM test, demonstrates MLE NPAP’s ability to achieve consistent, close-to-line-rate throughput. Ultra-Low Latency: The second chart, measuring a TCP_RR (Request/Response) test, highlights the ultra-high and deterministic transaction rates which is a key advantage that only a full-hardware network stack can deliver due to the required low round-trip-time (RTT) and low packet loss. Next: NPAP Implementation Details

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