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    A Simple Trick to Increase Your PCIe Bandwidth on AMD FPGAs

    FPGA DevTips, Network Acceleration
    A Simple Trick to Increase Your PCIe Bandwidth on AMD FPGAs Our Mission: If It Is Packets, We Make It Go Faster! And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet PCI Express (PCIe), CXL, OpenCAPI Data storage using SATA, SAS, USB, NVMe Video image processing using HDMI, DisplayPort, SDI, FPD-III. Today we are sharing the tips on how to maximize PCI Express (PCIe) throughput in  AMD FPGA devices using so-called PCIe Bifurcation. Depending on the architecture generation many modern AMD FPGA devices offer a PCIe Gen3 x16 / Gen4 x8 or PCIe Gen4 x16 / Gen5 x8 connection. The fastest supported PCIe lane speed is often only available for a reduced PCIe link width, resulting in no additional bandwidth when utilizing all sixteen PCIe lanes your FPGA card and host system may have. For some applications, this bandwidth is not enough. One option is to use PCIe bifurcation to increase the overall bandwidth for the application. A prerequisite is that PCIe bifurcation is supported by the CPU and motherboard BIOS, and the existence of at least two PCIe blocks in your FPGA device. PCIe bifurcation splits a PCIe slot into multiple independent PCIe links, connecting to separate PCIe Endpoints. For example one PCIe Gen5 x16 slot can be split

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    Testdrive the Future of Networking: Evaluate MLE’s FPGA-Powered TCP/IP Stack in the Cloud!

    FPGA DevTips, Network Acceleration, , ,
    Testdrive The Future of Networking: Evaluate MLE’s FPGA-Powered TCP/IP Stack in the Cloud! Our Mission: If It Is Packets, We Make It Go Faster! And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet PCI Express (PCIe), CXL, OpenCAPI Data storage using SATA, SAS, USB, NVMe Video image processing using HDMI, DisplayPort, SDI, FPD-III. In today’s fast-paced digital landscape, robust and efficient network communication is critical. For developers seeking to optimize network performance, MLE offers a groundbreaking solution: an FPGA-accelerated TCP/IP stack. Now, you can experience the power of this technology firsthand by evaluating it in our cloud-based environment, before committing to a hardware purchase. The Need for Speed: Overcoming Software Limitations Traditional software-based TCP/IP stacks often struggle to keep up with the demands of high-bandwidth, low-latency applications. Processing overhead can lead to bottlenecks and reduced efficiency. MLE’s FPGA-accelerated TCP/IP stack addresses these challenges by offloading network processing to dedicated hardware. The MLE Advantage: Hardware Acceleration for Optimal Performance Our Network Protocol Accelerator (NPAP) leverages the parallel processing capabilities of Field-Programmable Gate Arrays (FPGAs) to implement a full TCP/IP/UDP stack directly in hardware. This approach drastically reduces latency and maximizes throughput, offering a significant performance advantage over software-based solutions. Try Before You Buy: Cloud-Based Evaluation MLE understands the importance of thorough

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    Increase Speed and Save Resources with Simple Coding Style Changes

    FPGA DevTips, Network Acceleration, ,
    FPGA Programming – Increase Speed and Save Resources with Simple Coding Style Changes Table of ContentsFPGA Programming – Increase Speed and Save Resources with Simple Coding Style ChangesASIC vs. FPGA in Process AccelerationMLE Smart Process Redesign in FPGA Programming for Resource Saving and Speed Increasing ASIC vs. FPGA in Process Acceleration Compared to ASICs, FPGAs are a much more versatile option when it comes to accelerating processes with hardware, as an FPGA can be reconfigured and programmed as often as needed. However, one large benefit to ASICs is the possible maximum clock speed that can be reached. As its circuit is optimized for its specific function, it has a smaller footprint, resulting in a faster maximum clock speed. So one aspect of accelerating a process with FPGAs is not only just to redesign that process in hardware and hoping for faster results, but to smartly redesign that process to use as little hardware space as possible, resulting in a higher maximum clock speed. As engineers we know, there is always room for improvement, so we at Missing Link Electronics strive to continuously improve our existing product lineup. MLE Smart Process Redesign in FPGA Programming for Resource Saving and Speed Increasing In one of these development cycles, we encountered a simple, yet very

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