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A Simple Trick to Increase Your PCIe Bandwidth on AMD FPGAs Our Mission: If It Is Packets, We Make It Go Faster! And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet PCI Express (PCIe), CXL, OpenCAPI Data storage using SATA, SAS, USB, NVMe Video image processing using HDMI, DisplayPort, SDI, FPD-III. Today we are sharing the tips on how to maximize PCI Express (PCIe) throughput in AMD FPGA devices using so-called PCIe Bifurcation. Depending on the architecture generation many modern AMD FPGA devices offer a PCIe Gen3 x16 / Gen4 x8 or PCIe Gen4 x16 / Gen5 x8 connection. The fastest supported PCIe lane speed is often only available for a reduced PCIe link width, resulting in no additional bandwidth when utilizing all sixteen PCIe lanes your FPGA card and host system may have. For some applications, this bandwidth is not enough. One option is to use PCIe bifurcation to increase the overall bandwidth for the application. A prerequisite is that PCIe bifurcation is supported by the CPU and motherboard BIOS, and the existence of at least two PCIe blocks in your FPGA device. PCIe bifurcation splits a PCIe slot into multiple independent PCIe links, connecting to separate PCIe Endpoints. For example one PCIe Gen5 x16 slot can be split