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    Datasheet, NPAP Datasheet

    MLE NPAP Implementation Details

    Table of Contents

    MLE NPAP implements a full accelerator, hence all network protocol processing is running as digital logic. Because MLE NPAP does not rely on “soft” CPUs nor on external CPUs, MLE NPAP shows very low and deterministic latency. Tradeoff cost vs performance over chip resources.

    • Dataflow is full duplex 128 bits wide using AXI4 Stream. This enables high data throughput without “FPGA bloat” nor timing issues.
    • Control-flow uses AXI4 Lite register interfaces, along with a hardware abstraction layer (HAL), Linux device drivers and Python scripts for MLE NPAP administration.
    • MLE NPAP is intensively tested for performance and interoperability against many other TCP/UDP/IPv4 network stacks.
    • MLE NPAP brings its own 10G / 25G Low-Latency Ethernet MAC,
      but can interface with many Ethernet subsystems from the FPGA vendors.
    • MLE NPAP implements a complete TCP/UDP/IPv4 stack including functions like ARP, ICMPv4, IGMPv4, DHCP.
    • MLE NPAP is delivered with “Support IP blocks” including reference designs, design examples for setting MAC addresses and/or IPv4 addresses and/or TCP port numbers either from Programmable Logic / ASIC or via software running on a (Linux) host, either ARM or x86 based.
    • For each TCP connection that remains open at the same time, there shall be a dedicated instance of a TCP Core. An AXI4-Lite interface may be used to prioritize TCP sessions during runtime.
    • One and only one single instance of a UDP Core must be instantiated when UDP support is required. If there is no need to process UDP, then the UDP Core can be removed completely.
    • MLE NPAP is highly parameterizable to optimize for lowest FPGA resource needs while still delivering full functionality and performance: Number of UDP Cores (zero or one), number of TCP Cores (zero or many), for each TCP Core: Rx Buffer Size and, separately, Tx Buffer Size
    • Other than Rx and Tx buffers and some buffers for clock domain crossings, NPAP hardly uses any buffers at all, which results in very low and deterministic latency.
    • Your “Layer 7” Application can directly be connected to NPAP via AXI4 Stream which gives you the option of keeping all traffic inside the Programmable Logic / ASIC, and/or to interface with “software” running on (Linux) host, either ARM based or x86 based, via DMA.

    A hierarchical design philosophy is used to integrate MLE NPAP together with the auxiliary blocks. Related blocks are packaged together in a “support wrapper”. These are nested and joined within a top-level wrapper. Please refer to the NPAP Developer Documentation.

    At the highest level, a single NPAP based subsystem with NPAP Support IPs but with external MAC looks like this:

    NPAP Subsystem Top-Level

    Throughout this datasheet and our documentation we use the following color coding legend for certain blocks of functionality:

    NPAP Color Coding Legend

    Besides the number of TCP Cores, NPAP is highly parameterizable: Some parameters can be set at Compile-Time, others at Runtime, and some both ways.

    MLE NPAP Compile-Time Parameters

    NPAP makes use of VHDL Generics to parameterize certain functionality as well as the NPAP design structure (such as the number of TCP cores) at compile-time. 

    Here some examples:

    Parameter NameNPAP BlockDesign CategoryDocumented in
    ERD System Clock PeriodInfrastructureChip DesignProduct Guide: NPAP Kernel
    NPAP ARP Cache SizeKernelNW AdminProduct Guide: NPAP Kernel
    NPAP Maximum Frame SizeKernelNW AdminProduct Guide: NPAP Kernel
    Number of TCP SessionsKernelSystem-LevelProduct Guide: NPAP Kernel
    TCP TX Buffer SizeKernelNW AdminProduct Guide: NPAP Kernel
    TCP RX Buffer SizeKernelNW AdminProduct Guide: NPAP Kernel
    TCP TX Maximum Segment SizeKernelNW AdminProduct Guide: NPAP Kernel
    TCP RX Maximum Segment SizeKernelNW AdminProduct Guide: NPAP Kernel
    TCP TX Maximum Frame NumberKernelNW AdminProduct Guide: NPAP Kernel
    TCP Enable DGCTCP Demo AppTesting and DebugProduct Guide: NPAP Kernel
    UDP EnableKernelSystem-LevelProduct Guide: NPAP Kernel
    UDP TX Buffer SizeKernelNW AdminProduct Guide: NPAP Kernel
    …………

    A complete list of all Compile-Time Parameters and their use is available upon request. All are fully documented in the NPAP Developer Documentation.

    MLE NPAP Runtime Parameters

    NPAP behavior can be controlled at runtime via the Runtime Parameters. Typically, these are implemented via AXI-Lite registers. The complete set of all relevant registers is exported via a hardware abstraction layer (NPAP HAL) which then can be altered at runtime via the NPAP Administration & Control-Flow. 

    Here are some example run-time parameter:

    Parameter NameNPAP BlockDesign CategoryDocumented in
    NPAP Gateway IPKernelNW AdminProduct Guide: NPAP Kernel
    NPAP Local IPKernelNW AdminProduct Guide: NPAP Kernel
    MAC AddressKernel, MACNW AdminProduct Guide: NPAP Kernel
    NPAP Subnet MaskKernelNW AdminProduct Guide: NPAP Kernel
    TCP Session Data ProcessingTCP Demo AppSystem-LevelProduct Guide: TCP Demo App
    TCP Session Metadata ProcessingTCP Demo AppSystem-LevelProduct Guide: TCP Demo App
    TCP Session Loopback ModeTCP Demo AppSystem-LevelProduct Guide: TCP Demo App
    TCP Session Local PortTCP Demo AppNW AdminProduct Guide: TCP Demo App
    TCP Session Remote IPTCP Demo AppNW AdminProduct Guide: TCP Demo App
    …………

    A list of all Runtime Parameters and their use is available upon request. All are fully documented in the NPAP Developer Documentation.

    Next:
    NPAP Dataflow Block Diagram