Optimize MLE NPAP for Performance
Scaling performance for MLE NPAP is like any on-chip full accelerator: The wider the datapaths and the higher clock speed the better the throughput.
ASIC implementations can clock at 1 GHz, or faster (depends on with ASIC process you will be using) and power is not so much of an issue because MLE NPAP can be quite small (typ. less then 200k gates). For FPGAs, however, things are different, clock frequencies above 500 MHz may be hard to achieve.
MLE is constantly working with FPGA vendors to improve MLE NPAP clock frequency. While MLE NPAP originally was designed for ASIC implementation, MLE has adopted MLE NPAP for efficient implementation using modern FPGA fabric. Unlike other TCP stacks for FPGA, MLE NPAP features a 128 bit wide bi-directional datapath which puts MLE NPAP into a unique position for realizing high-bandwidth FPGA-based SmartNICs without “FPGA bloat”.
Larger bit widths, 512 bits or more, cause “FPGA bloat” which is wasting FPGA resources. Smaller bit widths, 64 bits or less, do require unrealistic high clock frequencies to deliver high line rates as the following table shows:
| 10 Gbps | 25 Gbps | 50 Gbps | 100 Gbps | |
|
32 bit
|
312.5 MHz
|
781.25 MHz
|
1,562.5 MHz
|
3,125.0 MHz
|
|
64 bits
|
156.25 MHz
|
390.625 MHz
|
781.25 MHz
|
1,562.5 MHz
|
|
128 bits
|
78.125 MHz
|
195.3 MHz
|
390.625 MHz
|
781.25 MHz
|
|
512 bits
|
19.5 MHz
|
48.8 MHz
|
97.7 MHz
|
195.3 MHz
|
Please refer to MLE Technical Brief TB20230523 “Put a TCP/UDP/IPv4 Turbo Into Your FPGA-SmartNIC” as this discusses pipelining the data paths to avoid “FPGA bloat”.