FPGA Design Integration
FPGA Design Integration of MLE NPAP
MLE NPAP is available as VHDL RTL source code or as a netlist suitable for synthesis by 3rd party and FPGA vendor tools which makes it possible to support almost any FPGA or ASIC target platform. The following toolchain versions have been tested at MLE:
| Version | AMD/Xilinx | Altera/Intel | Lattice Semi | Microchip |
|---|---|---|---|---|
| NPAP 2.5.0 (or newer) | Vivado 2022.2 Vivado 2024.2 | Quartus Prime Pro 22.4, 24.2 | Radiant 2024.2 | Libero 2024.2 |
| NPAP 2.4.5 (latest) | Vivado 2022.2 | Quartus Prime Standard 22.4 | n/a | n/a |
| NPAP 1.10.1 | Vivado 2018.3 | Quartus Prime Pro 22.1 | n/a | Libero 2021.2 |
Starting with version 2.5.0, NPAP is delivered as VHDL IEEE-1076 2008 RTL source code. This standard is fully supported by almost all modern FPGA toolchains, including those listed in the table above.
However, some older toolchains, such as Altera Quartus Prime Standard (required for legacy devices like Stratix V), do not offer full VHDL-2008 support. For these specific tools, the latest compatible release is NPAP v2.4.5.
MLE NPAP is Optimized for FPGA Pipelining
Starting with NPAP 2.0, RTL code has been optimized for FPGA pipelining such as Altera/Intel Hyperflex, Altera/Intel HyperFlex2 or AMD/Xilinx IMux. This avoids so-called “FPGA bloat”: Unlike other FPGA IP Cores which rely on 256 or even 512 bit wide datapaths, NPAP comes with more shallow combinatorial circuits to increase the FPGA clock speed, and thereby the on-chip throughput.
For more information please refer to MLE Technical Brief TB20230523.