Control-Flow View

MLE NPAP Control-Flow and Hardware Abstraction Layer

For administration and control at run-time, MLE NPAP implements so-called Runtime Parameterization and administration via an AXI-Lite register space. Access to this interface is exported through the so-called NPAP Hardware Abstraction Layer (HAL). Along with a Python library, NPAP HAL provides a high-level API for Linux software, utilizing swappable backends to communicate with the hardware across diverse environments, from SOC processing systems to remote workstations.

Here a list of connectivity choices for NPAP HAL:

1. Via USB-UART or USB-JTAG or USB-IIC
2. Via the FPGA-integrated Processing System which can be ARM, RISC-V, MicroBlaze, NIOS, etc
3. Via PCIe connection with the host CPU 
4. Via out-of-band Ethernet and UDP (on the roadmap)
5. Via in-band Ethernet and UDP (on the roadmap)

Besides NPAP HAL, MLE further provides a python based command-line tool, called npap-admin, that abstracts complex runtime parameterization into simple configuration file editing. Customers have been using npap-admin during evaluation and development, for Continuous Integration or in-the-field when NPAP-based products have been deployed.

Good design examples for Runtime parameterization and administration of NPAP are the so-called NPAP Evaluation Reference Designs (ERD) running on many off-the-shelf FPGA platforms. Please read 3.5. NPAP Evaluation Choices for more information.

MLE NPAP Admin via USB-UART or USB-JTAG

This mode of administration is very useful when using off-the-shelf FPGA development kits which feature a USB-to-UART connection which is then connected to a Linux workstation running Python.

In this setup, the NPAP HAL utilizes the Extensible FPGA Control Platform (XFCP) to bridge the USB connection to the AXI4-Lite register space on the FPGA.

Here an outline of the connectivity stack:

NPAP Admin
NPAP HAL with XFCP Backend
XFCP
Python Interpreter
Linux Kernel	SW
USB to UART
UART	HW
XFCP
AXI-4 Lite
NPAP ERD

MLE NPAP Admin via Embedded Processing System

This mode of administration is very useful when integrating MLE NPAP into a SoC-FPGA with embedded CPUs (“hard” or “soft”) where an embedded CPU runs Python under Linux.

In this setup, the NPAP HAL interacts with the NPAP ERD registers by accessing sysfs entries managed by a dedicated Linux driver. The connectivity stack, from the NPAP Admin CLI down through the Python HAL and the Linux kernel is outlined below:

NPAP Admin
NPAP HAL with Sysfs Backend
Python Interpreter
Sysfs
Linux Driver
Linux Kernel	PS
AXI-4 Lite	PL
NPAP ERD

MLE NPAP Admin via PCIe 

This mode of administration is very useful when using off-the-shelf PCIe Cards where the FPGA is connected via PCIe to a Linux host CPU which then can run Python.

In this setup, the NPAP HAL uses its sysfs backend to access the ERD’s AXI4-Lite register space. The register space gets mapped into the Linux filesystem via the Linux PCIe driver subsystem. The connectivity stack is outlined below:

NPAP Admin
NPAP HAL with XFCP Backend
Python Interpreter
Sysfs
PCIe Driver
Linux Kernel	SW
AXI-4 Lite	HW
NPAP ERD

MLE NPAP Admin via Out-of-Band Ethernet / UDP

This mode of administration is very useful when using networked FPGA boards which feature a separate Ethernet connection (typically 1 GigE) which is then connected to a Linux workstation running Python.

In this setup, the NPAP HAL utilizes the Extensible FPGA Control Platform (XFCP) to bridge the UDP Ethernet connection to the AXI4-Lite register space on the FPGA. The connectivity stack starting at npap-admin is outlined below:

NPAP Admin
NPAP HAL with XFCP Backend
XFCP
Python Interpreter
Linux Kernel	SW
UDP
ETH	HW
XFCP
AXI-4 Lite
NPAP ERD

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