MLE NPAP Dataflow Block Diagram
The following shows the dataflow view of an exemplary design integrating MLE NPAP with one UDP core and multiple TCP cores (3 for user-level plus 2 for Netperf), each with an example user application, plus Netperf (for bandwidth and latency benchmarking), plus network impairment (for Bit Error Rate Testing), plus diagnostics counters:
The example user applications serve as an example on how to send and/or receive data from programmable logic via TCP/UDP/IPv4. For TCP this logic is inside one (or more) TCP Wrappers which contain HDL code for handling the control and data flow:
- TCA – the TCP Command Application to open/close a TCP connection
- TDA – the TCP Demo Application which uses the TCA to control the TCP session and can forward data to and from external applications such as the DGC
- DGC – a Data Generator and Checker which can generate payload data for sending and at the same time can check received payload data
Similarly, for UDP this logic is inside the one (or more) UDP Wrappers which contain HDL code for handling the control and data flow:
- UDA – the UDP Demo Application which handles the control and data flow for one UDP port
- DGC – a Data Generator and Checker which can generate payload data for sending and at the same time can check received payload data
Optional diagnostic counters facilitate testing and tuning the quality of your system connectivity, including effects of signal quality issues in the physical layer. Please refer to the Product Guide of the NPAP Kernel for more details.
An optional Network Impairment block which sits between the Ethernet Link Layer and the Ethernet MAC mimics signal integrity issues by invalidating Ethernet packets based on an emulated bit error rate.
An optional Netperf block is a fully accelerated version of open source Netperf Version 2.6 which allows you to perform system-level performance analysis and benchmarking of bandwidth and latency / Round-Trip Times.
Obviously, all these optional blocks need extra FPGA resources, hence MLE NPAP has options to integrate them for engineering-level lab testing, or for in-field diagnostics throughout your product’s lifecycle (as needed sometimes), or for leaving them out.
For smaller FPGA devices, or when you need almost all FPGA resources for your own user logic, you can minimize resources by integrating a minimal MLE NPAP with just one single TCP core, for example, along with your TCP application:
Good examples for the dataflow implementation, parameterization and integration of MLE NPAP are the so-called MLE NPAP Evaluation Reference Designs (ERD) running on many off-the-shelf FPGA platforms. Please read below for more information.