MLE NPAP Resource Estimates for FPGA
Resource estimates are directly tied to the specific set of compile-time parameters: Therefore, a typical FPGA implementation which integrates MLE NPAP can range from as low as 10K LUTs to 1 million LUTs (for dozens of TCP cores).
MLE NPAP for AMD Versal AI Edge
The following table shows resources for AMD/Xilinx Versal AI Edge Series fabric (xcve2302-sfva784-1LP-e-S-es1) compiled with AMD/Xilinx Vivado/Vitis 2024.1 – instantiating the following design features:
- Ethernet block
- IPv4 block
- 1 UDP block
- 4 instances of TCP blocks
- Diagnostics blocks
MLE NPAP for AMD/Xilinx Ultrascale+ Series
The following table shows resources for AMD/Xilinx Zynq Ultrascale+ MPSoC ZU9EG compiled with AMD/Xilinx Vivado 2022.2 – instantiating the following design features:
- 10 GigE Low-Latency MAC from Fraunhofer HHI
- Ethernet block
- IPv4 block
- UDP block
- 10 instances of TCP blocks (2 used for netperf)
- TCP and UDP Diagnostics blocks
- 10 GigE Low-Latency MAC from Fraunhofer HHI
- Ethernet block
- IPv4 block
- UDP block
- 10 instances of TCP
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