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    Datasheet, NPAP Datasheet

    MLE NPAP Key Features

    With a focus on reliability and low, deterministic latency, MLE NPAP is a very resource-efficient network protocol accelerator platform for integration into ASIC and FPGA:

    • Interface to 1 / 2.5 / 5 / 10 / 25 / 40 / 50 / 100 / 200 / 400 Gigabit Ethernet
    • Full-duplex with 128 bit-wide bidirectional datapaths
    • Full line rate of 100 Gbps, or faster, per instance in ASIC
    • Full line rate of 70 Gbps, or faster, per instance in FPGA (depending on FPGA device)
    • Low and deterministic one-way latency (typ. 500 nanoseconds) with full TCP/UDP/IPv4 compliance
    • Network diagnostics functions (optional)
    • Network Impairment Generators (optional)
    • TCP session priority management (optional)
    • Transport Layer Security (TLS) (optional)
    • Time-Sensitive Networking (TSN) (optional)
    • Precision Time-Synchronization IEEE 1588-HA (optional)

    Designed for maximum flexibility, NPAP implements in RTL logic all the relevant network communication protocols:

    • IPv4 The core of the most standards-based networking protocols
    • TCP Reliable connectivity for direct secured connectivity
    • UDP Widespread protocol to enable simple direct or multicast communication
    • RRRRP Reliable, Rapid Request-Response Protocol based on Stanford HOMA
    • ICMPv4 Diagnostic protocol to validate connections
    • IGMPv4 Enables joining of multicast groups (optional)

    Due to its modularity and parameterizability, MLE NPAP can easily be enhanced with other proprietary and/or application specific protocols.

    With a focus on ASIC and FPGA resource efficiency, the 128 bit-wide bidirectional datapaths in combination with a pipelined architecture allow to scale throughput to line-rates of 70 Gbps, or faster, when using modern FPGA fabric, and to 100 Gbps, or faster, for ASIC implementations.

    Depending on the project’s needs, deliverables can be:

    • Complete HDL source code or netlist
    • Pre-validated FPGA project archive
    • Simulation testbenches and scripts for RTL verification
    • Comprehensive documentation and interfacing guide
    • Development & integration support

    NPAP addresses product longevity aspects and is available in versions which recently have been merged:

    • Version 2 (currently 2.9.0) for new ASIC and AMD/Xilinx Versal, Ultrascale+, Ultrascale, Altera/Intel Agilex-7, Agilex-5E and Stratix-10, Microchip PolarFire and Lattice Avant G/X development, includes many recent resource optimizations plus timing optimizations focused on pipelines in FPGA, including Altera/Intel HyperFlex and Intel HyperFlex2
    • Version 1 (currently 1.10.1) back-ports bug fixes from Version 2 for long-term customer support. Not recommended for new design starts!
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    Technical Specifications