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    Datasheet, NPAP Datasheet

    MLE NPAP Datasheet Overview

    MLE NPAP is a complete subsystem of a high-performance RTL based, standalone network stack featuring transparent handling of complete TCP/IPv4 and UDP/IPv4 protocol tasks, including packet encoding, packet decoding, acknowledge generation, link supervision, timeout detection, retransmissions and fault recovery. 

    MLE NPAP supports complete automatic connection control including tear up and tear down. Compute and manage retransmission timers as in RFC 6298. Transparent checksum generation and checksum checking, integrated flow control. RFC 9293 compatibility (TCP/IPv4 stack for Windows and Linux). 

    MLE NPAP has been optimized to ensure the best bandwidth-delay product performance for your application. To guarantee delivery of full performance and reliability Team MLE will support you in all engineering aspects:

    1. System-level architecture design where aspects such as mapping ingress / egress data streams to TCP sessions, or handling TCP’s congestion control, or optimizing the bandwidth-delay-product are handled in order to meet system-level bandwidth and latency requirements. 
    2. Chip-design and integration i.e. managing ASIC/FPGA resources, interfacing with the network PHYs and/or Multi-Gigabit Transceivers (MGT), handling on-chip streaming (such as AXI beats) while integrating MLE NPAP into your FPGA or ASIC device on your target hardware.
    3. Network administration which includes configuring TCP/UDP servers and clients as well as planning and administering the MAC and IPv4 addresses within each system as well as across all shipped units. 
    4. System verification, testing, diagnosing and debugging throughout your product’s lifecycle: From RTL simulation of NPAP integrated within your FPGA or ASIC over first engineering samples up to network diagnostics for products installed in the field.

    This datasheet aims to educate system architects, chip designers, verification engineers, product management and technical product support on how to plan, manage and make best use of MLE NPAP. 

    MLE NPAP follows a modular, parameterized implementation in VHDL / Verilog HDL. Modular means that blocks of functionality have been implemented by hierarchical HDL modules. Some of these modules can be instantiated multiple times – for example a TCP core which handles a so-called TCP connection – or not at all, when, for example, you may not need any TCP protocol support at all and wish to save FPGA resources.

    MLE NPAP can be tuned and optimized for your target application via around 100 parameters which 

    • are compile-time parameterizable, mostly via VHDL generics,
    • others are runtime parameterizable, typically via NPAP HAL – the Hardware Abstraction Layer between AXI Lite registers and Linux device drivers or Python scripts,
    • some are both, where you can set defaults at compile-time with options for change during runtime.

    MLE NPAP comes with extensive user-level and designer-level documentation, including how to architect, integrate, test, administer, and run this TCP/UDP/IPv4 Full Accelerator.

    Next:
    NPAP Key Features