Key-Value-Store (KVS) Accelerator
for Data Center Storage
Data Center Acceleration with FPGA-based Storage Accelerator
Xilinx, Fidus Systems and MLE have partnered to address the growing needs in High-Performance Computing and Data Center Acceleration to explore “unconventional” data-flow oriented FPGA-based system architecture for acceleration, hyperconvergence, object storage and in-memory compute.
The outcome of this is ZU19SN – a high-capacity, hyperconverged, networked storage node with a Zynq UltraScale+ ZU19EG MPSoC.
Featuring a network accelerator stack plus an out-of-order memory controller, high data throughput can be achieved while balancing between low-latency access and large storage capacities via integrated interfaces to connect to DDR3/DDR4 DRAM, Non-Volatile Memory Express (NVMe) Solid-State Disk (SSD), or SATA/SAS SSD or Harddisks (HDD).
MLE is a licensee of Xilinx and offers sub-licensing, technology support and complementary design services for integrating KVS Accelerator technology into your application for Data Center Acceleration.
- FPGA-based Key-Value load/store processing for data center server CPUs
- “Full Accelerator” in programmable logic for line-rate TCP/IP and Memcached processing
- Scalable performance to deliver processing speeds at 10, 25, 40, or 100 GigE line rates
- Total Server Power reduction via heterogeneous computing architecture
- Xilinx ZU19EP with dual NVMe m.2 SSDs and QSFP28 for dual 10/25/50/100 GigE
- Quad-Core ARM A53 w/ Xilinx PetaLinux
- Integrated System-on-Chip solution for Zynq Ultrascale+, or as PCIe-connected companion FPGA
- Modular implementation in HDL and C/C++ for Vivado HLS. Supports Xilinx HLx and SDx design flows
- Parameterizable for trade-offs between latency and capacity via DRAM, NVMe, SATA, SAS
- Fully networked with 10/25/40/100 GigE connectivity
- High-performance, low-power – many million responses per second (RPS) at over 200k RPS per Watt
- 13M RPS at 35 Watts board-level, measured at 10 GigE
- 100M RPS, extrapolated for 100 GigE
- Tested and benchmarked on object sizes between 128 Bytes to 1M Bytes
- Software-defined complete & customizable sub-system based on Xilinx IP cores for out-of-order memory controller, TCP/UDP/IP stack, hash table, DDR3/DDR4 DRAM, NVMe/SATA/SAS SSD and/or HDD interfaces
ZU19SN – a Zynq Ultrascale+ MPSoC
The ZU19SN Zynq UltraScale+ MPSoC Evaluation System is based on the Sidewinder-100 NVMe Storage Controller board from Fidus Systems:
- Xilinx ZU19EP w/ quad ARM A53 and dual ARM R5
- QSFP28 for dual 10/25/50/100 GigE
- PCIe Gen3 x16 or Gen4 x8 system i/f
- PCIe Gen3 x8 Host i/f
- 2x PCIe Gen3/4 NVMe m.2 SSDs
- 2x NGFF-8643 i/f for NVMe/SATA/SAS
- 2x 16GB SoDIMM w/ ECC, PS- and PL-attached
- Micro SD-Card, JTAG, UART, I2C, GPIO, …
The KVS Accelerator for Data Center Acceleration is available as a combination of Intellectual Property (IP) Cores, reference designs, and design integration services:
KVS Accelerator Device
|Integrated System-on-Chip solution, built on top of Xilinx Zynq-Ultrascale+ technology, integrating KVS acceleration with 10/25/100 GigE and SATA and/or NVMe, and others.
Based on NRE and unit volume
Intellectual Property (IP) Cores
|Single-Project or Multi-Project Use for Xilinx FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or HDL/C/C++ source code.
starting at $115,000.-
Application-specific R&D Services
|Advanced KVS acceleration R&D services with access to acceleration experts from MLE, Xilinx or Fraunhofer HHI.
| $1,480.- per
Frequently Asked Questions
ZU19SN is based on Xilinx Vivado 2016.4 and the matching Xilinx PetaLinux 2016.4.
Yes, you can! However, we noticed minor glitches with u-boot in 2017.1 and plan to test 2017.2. Please keep in mind that both versions,Vivado and PetaLinux, must match. If not you may run into problems because the PL hooks (aka hardware) may be incompatible with the PS hooks (aka software), and again, may be incompatible with the HDF file. Therefore, Xilinx (and MLE) recommends to use identical versions for both! Zynq SSE is closer to the other hard IP core I/O functions inside the Zynq Processing System (PS), like UART or SDIO: It is fully instantiated and ‘frozen’ and cannot be altered – other than you are able to change the pin assignment.
The Sidewinder-100 board from Fidus Systems is populated with an engineering sample ES2 of the Xilinx ZU19EG device. Please ensure that you have enabled beta device support. Please check back with our documentation on instruction for enabling beta device support.
Yes, this project is all about collaboration. So, you will receive source code & scripts for the PetaLinux project plus for everything that is not a 3rd-party IP core.