Past Projects of FPGA and IP Core Design
MLE has extensive experience in FPGA and IP Core Design for a wide range of advanced applications. Our past projects can be found in the following areas:
TCP/UDP/IP Full Acceleration for Medical Imaging
Integrate and enhance Network Protocol Accelerator Platform (NPAP) for up to 50 Gbps line rates; aggressive resource optimization using asymmetric packet buffer schemes; enhance for application-specific Quality-of-Service (QoS) behavior.
TCP/UDP/IP Full Accelerator Code Migration to Microchip Polarfire
Migrate Fraunhofer TCP/UDP/IP VHDL code to PolarFire and adjust VHDL code base for non-volatile Flash-based structures; integrate with 5 Gigabit Ethernet and 10 Gigebit Ethernet subsystem; test on MPF300 Development Kit.
25G TCP/IP Network Protocol Acceleration for AMD/Xilinx UltraScale+ RFSoC
Ported Fraunhofer HHI TCP/IP and UDP Full Accelerator to the AMD/Xilinx RFSoC ZCU111 platform, integrated with 25G PCS/PMA subsystem (AMD/Xilinx PG210 v2.5), verify and test 25 Gbps linerate performance, latency and interoperability against Mellanox Technologies ConnectX-4 Lx EN.
UDP Acceleration for Automotive Datalogger
Integrate 3rd party Fraunhofer HHI UDP/IP stack, implement custom data download and control protocol in AMD/Xilinx Zynq-7100.
TCP/IP Acceleration using AMD/Xilinx Virtex-6 and Virtex-7
Integrate 3rd party Fraunhofer HHI TCP/IP stack, clock domain partitioning to make timing closure for very high device utilization.
10 GigEthernet Network Protocol Accelerator
Modularization of 3rd party IP core in VHDL, adaptation to IP core centric design flow in AMD/Xilinx Vivado 2014.4, integration with AMD/Xilinx Zynq All-Programmable SOC via AXI4 interfaces, PetaLinux device driver deleopment, implementation of test environment based on AMD/Xilinx ZC706 Development Kit.
SATA Storage Subsystem for SSD Array
Integrate 3rd party ASICS World-Services SATA IP Core into AMD/Xilinx Zynq-7100 for automotive datalogging onto SSD Array, implement and test RAID-style striping architecture to achieve high SSD read/write performance.
Multi-Port SATA-6G Host-Controller
System-on-Chip architecture design, on-chip connectivity of 3rd party SATA Host Controller and DMA soft IP core with FPGA-based PCIe hard IP end-point, implementation in Altera Stratix-IV 230 and AMD/Xilinx Virtex-7 485, SATA and PCIe device driver development for Linux.
Protocol Accelerators for AHCI and NVM-Express
FPGA implementation in AMD/Xilinx Virtex-7 690, Linux device driver and application software development under Ubuntu Linux, connectivity for Solid-State-Disks (SSD) running Advanced Host-Controller Interface (AHCI) and Non-Volatile Memory Express (NVMe) protocols.
Automotive / Time Sensitive Network (TSN)
ADAS communication infrastructure based on AMD/Xilinx Zynq UltraScale+ MPSoC
PCB-level design support, bring-up and interface testing of a Zynq UlraScale+ MPSoC based ADAS communication infrastructure. Architecture design and implementation of PCIe and NTB based communication infrastructure and data stream distribution from sensors to compute modules.
Speed-up FPGA Boot Times for Automotive
Using SelectMap (AMD/Xilinx XAPP583) implement faster FPGA config & boot for Artix-200, Lattice MachXO2 CPLD and QSPI Flash memory interfaces.
Automotive multi-camera vision system based on AMD/Xilinx Zynq and Zynq UltraScale+ MPSoC
System-level software architecture design; FPGA platform development using multi-input, multi-buffer Video-DMA and HDMI monitor output; porting Lukas-Canade Optical Flow IP core; C++ software acceleration using AMD/Xilinx Vivado HLS and AMD/Xilinx SDx toolchain.
Automotive heterogeneous compute platform for Radar / Lidar image processing on AMD/Xilinx Zynq UltraScale+ MPSoC
Configuration and testing of base AMD/Xilinx PetaLinux system (FSBL, kernel, DTS); BroadR-Reach PHY Linux driver development; development of shared memory buffers and IPI communication between Linux on ARM Cortex A53 and AutoSAR/bare metal on ARM Cortex R5; system clocking architecture and design “hardening” via XMPU, XPPU.
PCI Express (PCIe)
PCIe Card Implementation Using Microchip PolarFire FPGA
Pro-active obsolescence management and hardware re-design of PCI card; support PCB design team with FPGA pin planning for industrial interfaces; migrate legacy FPGA subsystems from AMD/Xilinx Spartan 6 to Microchip PolarFire; PCIe subsystem integration which ensure software-level compatibility with legacy PCI software and device drivers; hardware bringup and test.
PCI Express Gen3 x8 Bridge Architecture
Integration of 3rd party PCIe Gen3 soft IP core for PCIe Up- and Down-Switch-Ports, close collaboration with IP core vendors and FPGA vendor, PCIe BAR architecture design, interfacing with COM Express Intel CPU module running Ubuntu Linux with Long-Term Support, Linux device driver development.
PCI Express Gen2 x2 Device
Integration of customer-provided functionality with FPGA hard IP end-point, BAR mapping for Intel Qseven-based embedded system, device driver and PCIe test development for Linux, seamless migration from Altera Arria-V GX starter kit to customer target hardware.
Many-Sensor Pre-Processing System Using AMD/Xilinx KRIA System-on-Module (SoM)
Design system-level architecture; PCB schematics design for custom baseboard using Altium, collaborate via Altium Live; pin planning for HDMI-to-LVDS display output.
Implementation of AMD/Xilinx IDELAY based fast 3 GS/s ADC parallel LVDS interface
Implemented for AMD/Xilinx Virtex 7; use of multiple LVDS pairs with 750 Mb/s each; use of IDELAY primitives for data eye analysis and sampling point adjustment (initial training and tracking/adjustment over wide temperature range).
Custom FPGA and IP Core Design Service
Application-specific FPGA to FPGA communication protocol
Implemented for AMD/Xilinx Zynq Ultrascale+ MPSoC and AMD/Xilinx 7-Series devices; use of LVDS pins with 8b10b coding and scrambling for a data rate of 100 Mb/s; use of IDELAY primitives or fast clocked Flip Flops for data eye analysis and sampling point adjustment (training); Flow control support for packetized upper layer communication protocol.
AMD / Xilinx Long Term Support
AMD / Xilinx XAUI IP Core Long-Term Support
Receive and augment AMD/Xilinx XAUI and RXAUI IP core; implement RTL simulation and verification environment using Questa / ModelSim from Mentor Graphics / Siemens EDA; migrate from legacy FPGA devices to AMD/Xilinx UltraScale and AMD/Xilinx UltraScale+ multi-gigabit transceivers.
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