The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.
The German Fraunhofer Heinrich-Hertz-Institute has developed patent pending TCP/IP and UDP/IP acceleration technology, and has approached MLE to market this technology as a Network Protocol Acceleration Platform (NPAP) for ASIC and FPGA, world-wide.
Effectively offloads hyper-converged data center storage server CPUs from KVS processing. Combines dataflow processing architecture for performance scalability with the size, weight and power advantages of a single-chip hetero-geneous multi-core processing system-on-chip (Xilinx Zynq Ultrascale+ MPSoC).
Originating from Xilinx, the XPS USB 2.0 EHCI Host Controller is now available in Revision 2.00a and allows users to connect almost any Xilinx FPGA with full-speed and/or high-speed USB devices, for example for human-machine interface applications, cameras, and storage.