Mixed Signal FPGAs
Mixed Signal FPGAs
MLE’s patent pending Mixed Signal FPGA solutions make Delta-Sigma-Modulator technology applicable to your next Embedded System project.
When it comes to processing legacy data protocols FPGA offer very cost efficient alternatives to the – sometimes hard to get – original circuits. MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.
|Standard Approach||MLE Mixed Signal FPGAs|
Core Benefits of Mixed Signal FPGAs
- Reduce your hardware footprint and parts count
- No active peripheral ICs required
- Efficient post-processing with low FPGA resource cost.
- Highly reconfigurable analog-to-digital converter (ADC) / digital-to-analog converter (DAC) parameter setting
- Design flexibility: „one more I/O“
- Greatly reduce costs when applying multitudes of analog I/O channels
- Reasonable I/O precision, more than sufficient for most of today’s analog applications in Embedded Systems
- ADC sample rate: up to 200 kS/s
- ADC resolution: up to 11 bits ENOB
- Flexible data acquisition and monitoring systems
- Cost-efficient embedded systems with many sensor inputs
- Voltage-based actuator control, DC motor control
- Audio Output – that FPGA sounds great!
- Integrated microcontrollers with reduced risk of parts obsolescence
- Amplitude-Modulated (AM) protocol processing, for example IRIG
MLE provides a suite of Intellectual Property (IP) Cores, reference designs, and design tools within a Mixed-Signal design suite. This complements the “soft” ADCs and DACs with optimized-for digital signal filtering and conditioning which takes the burdon of parametrization away from the user.
MLE provides a three-phase product integration roadmap for new customers:
|Product Name||Deliverables||Example Pricing|
|Requirements & Feasibility Analysis||Integration service into customer project;
|Production License||IP license for one defined product; worldwide, fully paid up for, perpetual; up to 3 parametrizations, up to 33 channels per FPGA device family.||Inquire|