MLE Silver Sponsor of Xilinx Developers Forum 2019 in San Jose, CA

October 1-2, 2019, Missing Link Electronics is a Silver Sponsor of the Xilinx Developers Forum (XDF) in San Jose, CA, where we will be presenting solutions for FPGA Acceleration and for Security / ARM Trusted Execution Environment (OP-TEE). Please stop by and visit us at Booth 35. 

Click here for more information and how to register for XDF 2019.

 


 

3rd Workshop "Programmable Processing for the Autonomous / Connected Vehicle"

On July 17th 2019 the 3rd workshop on using FPGAs and ACAP for automotive ADAS and autonomous vehicles took place. Once more it was an excellent event with high-quality presentations and participants who showed great interest.

Click here to get an impression of our third workshop.

 


 

Lunch & Learn at EDA Direct Tuesday June 25th, 2019

MLE will participate in "Designing High-Performance ECU and Signal Integrity Analysis in Autonomous Vehicles" at a Lunch & Learn organized by EDA Direct. See here for more information and how to register for this event.

Read the MLE Technical Brief Tool Options When Debugging an FPGA-Based ECU for Autonomous Driving.

 


Presentation at PCI-SIG Developers Conference 2019

MLE presents "Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles" at the PCI-SIG Developers Conference 2019.

 (download slides) or visit our technical publications.


MLE Featured Premier Xilinx Alliance Partner

Xilinx features Missing Link Electronics as a Premier Partner offering IP, Design Services and Software for key markets Aerospace & Defense, Automotive, Data Center, Industrial, Wired Communications, Wireless Communication.

Solutions and services from Missing Link Electronics include Security (OP-TEE), crypto subsystems, connectivity (PCIe, Ethernet, USB, SATA, NVMe) IP integration, camera/lidar/radar data acquisition and aggregation processing, Functional Safety, TCP/UDP/IP Full Accelerators, Key-Value-Store Accelerators, Digital Signal Processing IP (PAM/QAM Multi-format mapper, OFDM transmitter, WOLA channelizer, Adaptive time-domain equalizer, FFT), PetaLinux Design Service.


 

Embedded World Exhibition 2019-Xilinx Booth

TUE FEB 26 - THU FEB 28 - Exhibition Nuremberg - live demo at the Xilinx Booth

Booth 3A-235Zync UltraScale+ RFPSoC – Software Defined Radio

This Software Defined Radio demonstration showcases the Zynq® UltraScale+™ RDSoC multi-giga-sample RF data converters, and soft-decision forward error correction (SD-FEC), integrated into a SoC architecture. Complete with an ARM® Cortex™-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwith in a Zynq UltraScale+ device, this family provides a comprehensive FR signal chain for wireless, cable access, test & measurement, early warning / radar, and other high performance FR applications.  


 

New Lab Space for Customer System Hardware

WED JAN 4 2019

Responding to needs for additional engineering lab space for customer system hardware setup and integration testing, Missing Link Electronics expands office space in Neu-Ulm, Germany. 


 

Embedded World Exhibition 2019

TUE FEB 26 - THU FEB 28 - Exhibition Nuremberg

In addition to our technical presentations at Embedded World 2019, MLE's FPGA experts will be available at Booth 3A-430 in Hall 3A. More information coming soon.


 

US Patent 10,140,049 on Functional Safety

WED NOV 27 2018

In the area of Functional Safety for Reconfigurable Systems, Missing Link Electronics has been awarded US Patent 10,140,049. This patent is titled "Partitioning Systems Operation in Multiple Domains".

 


 

Embedded World Conference 2019 - Technical Presentations

WED FEB 27, 2019 - Embedded World Conference 2019 at MCC Ost:

MLE FPGA experts will present at Embedded World Conference: Session 5.4 "Power Supply", MLEs' Director of Applications Andreas Schuler presents "OP-TEE – An Intro to a Trusted Execution Environment", beginning: 4:00 PM. Cedrik Bock, Design Engineer (M-Sc. EE) at MLE, presents "System-Level Modeling of Heterogeneous Compute Architectures for NVMExpress Protocol Acceleration" at Conference Session 10.2 II SoC II EDA II, beginning 4:00 PM.