Past Projects

TCP/IP Acceleration using Xilinx Virtex-6 and Virtex-7

Integrate 3rd party Fraunhofer HHI TCP/IP stack, clock domain partitioning to make timing closure for very high device utilization.

Single-chip solutions for a digital Pseudo Noise Radar using Xilinx Zynq UltraScale+ RFSoC

Architecture exploration to reach 30 FPS performance goal. FPGA development using HDL and High-Level Synthesis (Vivado HLS) for buffering and data-in-motion reorg using external PL-attached DDR4 RAM, FFTs, correlation, ARM A53 software under Linux for data IO and visualization.

NVMe stream recording using FPGA and SSD

Integrate Xilinx plus in-house plus and open-source IP cores into Virtex-7 based Micro-TCA off-the-shelf hardware. Evaluation SSD vendors for extended temperature ranges and NVH. Diagnose and test NVMe write performance for lossless recording.

OS integration and hardening in an multi FPGA NUMA architecture on Xilinx Ultrascale+ MPSoC:

Integrate OS into multi FPGA architecture; USB and PCIe error mitigations on OS level as well as Hardware (FPGA) level; System turn-on and bringup and analysis to specification.

Time-Synchronized Audio Transmission based on Xilinx Zynq Ultrascale+ MPSoC:

Reception of IRIG-B12x, IRIG-B00x and HaveQuick time information; Transmission of sets of audio samples at software defined points in time; Augmentation of received audio samples with timestamp information; Xilinx PetaLinux drivers and integration.

ADAS communication infrastructure based on Xilinx Zynq UltraScale+ MPSoC:

PCB-level design support, bring-up and interface testing of a Zynq UlraScale+ MPSoC based ADAS communication infrastructure. Architecture design and implementation of PCIe and NTB based communication infrastructure and data stream distribution from sensors to compute modules.

RFSoC with GNU Radio:

Design and implement a proccessing chain to access the high speed DAC and ADC of the PFSoC. This chain can be accessed by GNURadio, a open source software defined radio implementation. To acces the processing chain, MLE implemented a configureable sink and source block for GNURadio.

Datacenter Storage Node based on Xilinx Zynq Ultrascale+ MPSoC:

PS- and PL-attached NVMe connectivity using Xilinx IP cores and Xilinx PetaLinux; integration and test of 10G/25G Ethernet and Network Protocol Acceleration; integration and test of Xilinx NVMe-over-fabric technology.

Xilinx PetaLinux Designflow for Xilinx Zynq Ultrascale+ MPSoC:

Educate and support customer with software development and designflow aspects for ZU+ MPSoC; set up Xilinx PetaLinux build environment under Unix, integrate into agile development process.

Cloud migration of an FPGA-accelerated Deep-Learning application to Amazon AWS EC2 F1 instance:

Migrate existing embedded system for FPGA-accelerated Deep-Learning to Amazon AWS EC2 F1 FPGA instance; adopt FPGA designflow to AWS based FPGA designflow; port embedded Linux with Jupyter Python subsystem to AWS EC2 F1 Linux AMI; integrate and test FPGA design and port to AWS AFI; setup and register in Amazon AWS marketplace.

Automotive multi-camera vision system based on Xilinx Zynq and Zynq UltraScale+ MPSoC:

System-level software architecture design; FPGA platform development using multi-input, multi-buffer Video-DMA and HDMI monitor output; porting Lukas-Canade Optical Flow IP core; C++ software acceleration using Xilinx Vivado HLS and Xilinx SDx toolchain.

Automotive heterogeneous compute platform for Radar / Lidar image processing on Xilinx Zynq UltraScale+ MPSoC:

Configuration and testing of base Xilinx PetaLinux system (FSBL, kernel, DTS); BroadR-Reach PHY Linux driver development; development of shared memory buffers and IPI communication between Linux on ARM Cortex A53 and AutoSAR/bare metal on ARM Cortex R5; system clocking architecture and design "hardening" via XMPU, XPPU.

Heterogeneous Data Processing for a 4-channel, 5.6 Gbps Wind-Lidar system:

High-speed analog ADC / DAC interfacing via JESD204B; FPGA based proprocessing and decimation filtering in Xilinx Virtex-7 690T FPGA; FFT and cross-correlation filter in TI TMS320C6678 DSP; Windows and Linux based GUI design on x86 CPU module in micro-TCA form-factor.

PCI-Express Gen3 Test & Measurement System in Xilinx Virtex-7 690T FPGA:

Diagnostics for PCIe low-power states; acceleration of read/write for PCIe address space modules; design of integrated Bit-Error-Rate Tests (iBERT); PCIe upstream and downstream switch modules; diagnostics for PCIe multi-lane de-skew; PCIe specification conformity analysis.

Tunneling of PCI-Express Transaction-Layer-Packets (TLP) with TCP/IP over 10G Ethernet:

Design and test of a working proof-of-concept implementation on Xilinx Zynq-7000 (ZC706); integration of 3rd-party full accelerators; latency analysis at PCIe clock accuracy using Tracer packets and Xilinx Integrated Logic Analyzer (ILA).

CPLD development under SIL-2:

Implementation of Fully synchronous design in VHDL, interface and data processing with 3D optical sensor, set-up of verification and validation environment, implementation in Lattice MachXO3 CPLD, close collaboration with customer and FPGA vendor to meet TÜV certification for Safety-Integrity Level 2 (SIL-2).

IO-Link Device Stack implementation on micro-controller:

Requirements analysis based on IO-Link specification Version 1.1.1, implementation of a design and validation environment in SystemC, 8-bit micro-controller programming in ANSI C/C++ for Atmel ATmega168, porting and 32-bit optimization for ST STM32 micro-controller.

Multi-Port SATA-6G Host-Controller:

System-on-Chip architecture design, on-chip connectivity of 3rd party SATA Host Controller and DMA soft IP core with FPGA-based PCIe hard IP end-point, implementation in Altera Stratix-IV 230 and Xilinx Virtex-7 485, SATA and PCIe device driver development for Linux.

PCI Express Gen3 x8 Bridge Architecture:

Integration of 3rd party PCIe Gen3 soft IP core for PCIe Up- and Down-Switch-Ports, close collaboration with IP core vendors and FPGA vendor, PCIe BAR architecture design, interfacing with COM Express Intel CPU module running Ubuntu Linux with Long-Term Support, Linux device driver development.

Wireless HDMI Adapter for SDI-3G:

System-, FPGA- and PCB-level design review, enhancement of streaming video system to support 1080p, 1080i, 720p, 480p and 576i video formats, implementation of anti-jitter solution in HDL, FPGA design using Altera Video IP Suite for Cyclone IV E device, development of system-level test environment based on COTS modules, close collaboration with FPGA distributor.

Protocol Accelerators for AHCI and NVM-Express:

FPGA implementation in Xilinx Virtex-7 690, Linux device driver and application software development under Ubuntu Linux, connectivity for Solid-State-Disks (SSD) running Advanced Host-Controller Interface (AHCI) and Non-Volatile Memory Express (NVMe) protocols.

Multi-Port SAS-12G Initiator:

Integration of multiple instances of 3rd-party SAS Initiator and DMA soft IP cores in existing Xilinx Virtex-7 FPGA design, close collaboration with 3rd-party IP core vendor, on-chip and off-chip analysis for high-speed serial transceiver connectivity, close collaboration with FPGA vendor for migration from Xilinx GTX to Xilinx GTH transceiver technology.

PCI Express Gen2 x2 Device:

Integration of customer-provided functionality with FPGA hard IP end-point, BAR mapping for Intel Qseven-based embedded system, device driver and PCIe test development for Linux, seamless migration from Altera Arria-V GX starter kit to customer target hardware.

10 GigEthernet Network Protocol Accelerator:

Modularization of 3rd party IP core in VHDL, adaptation to IP core centric design flow in Xilinx Vivado 2014.4, integration with Xilinx Zynq All-Programmable SOC via AXI4 interfaces, PetaLinux device driver deleopment, implementation of test environment based on Xilinx ZC706 Development Kit.

OpenAMP for Xilinx Zynq:

Implementation of Non-Uniform Memory Access (NUMA) architecture, integration of Mentor OpenAMP Asynchronous Multi-Processing with interfaces between real-time RTOS on first core and PetaLinux on second CPU core, integration of Diskrete Fourier-Transformation (DFT) block in Zynq Programmable Logic (PL) with ARM A9-MP multi-core CPU via AXI-4 on-chip connect.

Video-for-Linux (V4L2):

Integration of 3rd party PCIe and Video-DMA IP cores in Xilinx Zynq-7000 All-Programmable SOC, PCIe connectivity to Intel CPU under Linux, Linux device driver and application software development for frame-buffer and frame-grabber device functionality.

USB 2.0 Host Controller:

Design analysis and functionality enhancements for MicroBlaze and PetaLinux based embedded system for USB-attached storage application, porting from Big-Endian IBM Processor-Local-Bus (PLB) to Little-Endian ARM AXI standard, close collaboration between customer and FPGA vendor during migration to TÜV-certified FPGA tool chain and design flow.

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