CPLD development under SIL-2:
Implementation of Fully synchronous design in VHDL, interface and data processing with 3D optical sensor, set-up of verification and validation environment, implementation in Lattice MachXO3 CPLD, close collaboration with customer and FPGA vendor to meet TÜV certification for Safety-Integrity Level 2 (SIL-2).
IO-Link Device Stack implementation on micro-controller:
Requirements analysis based on IO-Link specification Version 1.1.1, implementation of a design and validation environment in SystemC, 8-bit micro-controller programming in ANSI C/C++ for Atmel ATmega168, porting and 32-bit optimization for ST STM32 micro-controller.
Multi-Port SATA-6G Host-Controller:
System-on-Chip architecture design, on-chip connectivity of 3rd party SATA Host Controller and DMA soft IP core with FPGA-based PCIe hard IP end-point, implementation in Altera Stratix-IV 230 and Xilinx Virtex-7 485, SATA and PCIe device driver development for Linux.
PCI Express Gen3 x8 Bridge Architecture:
Integration of 3rd party PCIe Gen3 soft IP core for PCIe Up- and Down-Switch-Ports, close collaboration with IP core vendors and FPGA vendor, PCIe BAR architecture design, interfacing with COM Express Intel CPU module running Ubuntu Linux with Long-Term Support, Linux device driver development.
Wireless HDMI Adapter for SDI-3G:
System-, FPGA- and PCB-level design review, enhancement of streaming video system to support 1080p, 1080i, 720p, 480p and 576i video formats, implementation of anti-jitter solution in HDL, FPGA design using Altera Video IP Suite for Cyclone IV E device, development of system-level test environment based on COTS modules, close collaboration with FPGA distributor.
Protocol Accelerators for AHCI and NVM-Express:
FPGA implementation in Xilinx Virtex-7 690, Linux device driver and application software development under Ubuntu Linux, connectivity for Solid-State-Disks (SSD) running Advanced Host-Controller Interface (AHCI) and Non-Volatile Memory Express (NVMe) protocols.
Multi-Port SAS-12G Initiator:
Integration of multiple instances of 3rd-party SAS Initiator and DMA soft IP cores in existing Xilinx Virtex-7 FPGA design, close collaboration with 3rd-party IP core vendor, on-chip and off-chip analysis for high-speed serial transceiver connectivity, close collaboration with FPGA vendor for migration from Xilinx GTX to Xilinx GTH transceiver technology.
PCI Express Gen2 x2 Device:
Integration of customer-provided functionality with FPGA hard IP end-point, BAR mapping for Intel Qseven-based embedded system, device driver and PCIe test development for Linux, seamless migration from Altera Arria-V GX starter kit to customer target hardware.
10 GigEthernet Network Protocol Accelerator:
Modularization of 3rd party IP core in VHDL, adaptation to IP core centric design flow in Xilinx Vivado 2014.4, integration with Xilinx Zynq All-Programmable SOC via AXI4 interfaces, PetaLinux device driver deleopment, implementation of test environment based on Xilinx ZC706 Development Kit.
OpenAMP for Xilinx Zynq:
Implementation of Non-Uniform Memory Access (NUMA) architecture, integration of Mentor OpenAMP Asynchronous Multi-Processing with interfaces between real-time RTOS on first core and PetaLinux on second CPU core, integration of Diskrete Fourier-Transformation (DFT) block in Zynq Programmable Logic (PL) with ARM A9-MP multi-core CPU via AXI-4 on-chip connect.
Integration of 3rd party PCIe and Video-DMA IP cores in Xilinx Zynq-7000 All-Programmable SOC, PCIe connectivity to Intel CPU under Linux, Linux device driver and application software development for frame-buffer and frame-grabber device functionality.
USB 2.0 Host Controller:
Design analysis and functionality enhancements for MicroBlaze and PetaLinux based embedded system for USB-attached storage application, porting from Big-Endian IBM Processor-Local-Bus (PLB) to Little-Endian ARM AXI standard, close collaboration between customer and FPGA vendor during migration to TÜV-certified FPGA tool chain and design flow.