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      PCI Express over IP, Accelerated – A Low Latency Fabric for System-of-Systems

      Technical Publications,
      Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg
      PCIe IP - PCI Express over IP Architecture

      PCIe Over IP is a networking breakthrough developed by Missing Link Electronics (MLE) and Fraunhofer HHI that extends native PCI Express (PCIe) interconnects beyond local circuit board limits across standard Gigabit TCP/IP networks. By using hardware-based FPGA TCP/IP Acceleration Engines (TOE), PCIe Transaction Layer Packets (TLPs) are encapsulated and streamed over standard copper or fiber Ethernet infrastructure with zero host CPU overhead, sub-microsecond latency, and full software transparency.

      These FPGA-based full accelerators enable reliable tunneling of PCI Express of existing LAN. This approach is transparent to the CPU Root Complex and Operating System and can be scaled to match 1/10/25/40 GigE line rates.

      PCIe over IP Presentation