# Network Acceleration
Fraunhofer HHI and MLE to Collaborate on 25/50G Ethernet MAC
German Fraunhofer Heinrich-Hertz-Institute (HHI) and MLE collaborate to enhance Fraunhofer HHI's Low-Latency Ethernet MAC and TCP/IP Stack to support Xilinx UltraScale+ GTY Transceiver Technology for 25/50 Gig Ethernet.
FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols
Presentation at the DESY MTCA Workshop for Industry and Research in Hamburg Hardware-acceleration of networking protocol stacks, enabled to be optimized for specific applications and underlying network protocols, going beyond…
High-Level Synthesis for FPGA Implementation of Network Protocols
Presentation at the Embedded World Conference 2015 Combining network protocol acceleration technology from Fraunhofer HHI with Vivado HLS for programming Xilinx Zynq All Programmable SoC. (download slides)
Low-Latency Networking for Systems-of-Systems
Presentation at Embedded World Conference 2014 How hardware acceleration helps reducing latency and increasing bandwith. (download slides)