# Network Acceleration
MLE Updates TCP/UDP/IP Network Protocol Accelerator Platform
MLE has updated NPAP, the Network Protocol Accelerator Platform based on Fraunhofer HHI’s TCP/UDP/IP stack for ASIC and FPGA. Work includes enhancements for performance and interoperability when connecting to Microsoft…
10 GigE TCP/IP Stack for High-Speed Camera Transport
Presentation at FPGA Conference Europe in Munich, Germany, July 5-7, 2022 MLE presents NPAP, a TCP/IP full accelerator from Fraunhofer HHI, for use in Multi-Gigabit High-Speed Camera Image Transport. With…
Platform Choices for FPGA-Based In-Network Compute Acceleration
Presentation at SmartNICsSummit 2022, April 26-28, 2022 FPGA-based SmartNICs can provide significant benefits by offloading network data processing off of CPU cores, data-in-motion processing, effectively enabling In-Network Compute. However, FPGA…
Network Element Virtualization (NEV) With FPGA
To enable Network Element Virtualization (NEV) for telefommunications Algoblu Co. L.t.d. from Ottawa, Ontario, Canada, has worked with Missing Link Electronics (MLE) to design and test FPGA-based turnkey solutions. With…
MLE NPAC-40G Now Runs CORUNDUM System Stack
MLE has ported and tested a full system stack based on CORUNDUM for NPAC-KETCH, CORUNDUM is a vendor-neutral open source high-performance FPGA-based SmartNIC development platform. NPAC-KETCH is a FHHL PCIe…
MLE NPAC-40G – A Cost-Efficient PCIe SmartNIC Solution
MLE has partnered with Fraunhofer HHI and Elemaster Germany to provide the industry-proven TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) in form of NPAC-40G, a PCIe Network Protocol Accelerator Card. NPAC-40G…
MLE Releases NPAP TCP/UDP/IP Stack Version 1.8.0
MLE has released Version 1.8.0 of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. Changes include fixes for UDP, padding for Ethernet frames smaller than 60 Bytes and an increase…
NPAP RTL Simulation Demonstrates Low-Latency TCP/IP
MLE has complemented NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI, with an RTL Simulation environment for Xilinx Vivado ISim and for the Questa Advanced Simulator from Siemens EDA. This…
MLE & Intel PSG Optimize NPAP for Intel HyperFlex Architecture
As the outcome of joint engineering collaboration between Intel PSG and MLE Germany, an new version of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI was released by MLE. This…
CORUNDUM – From a NIC to a Platform for In-Network Compute
Presentation at FOSDEM’22, February 5-6, 2022 This joint presentation between Alex Forencich, UC San Diego, and Ulrich Langenbach, MLE, provides an introduction to the corundum project, implementing a 100 GbE…