# NPAP
MLE and Trenz Verify the AMD/Xilinx Versal™ AI Edge Device and Accelerate Networking and Storage with 10G/25G/50G/100G TCP/IP Core
MLE and Trenz Electronic, both Premier Members of the AMD Adaptive Computing Partner Program, have collaborated and worked on Trenz’s new TE0950 AMD/Xilinx Versal™ AI Edge Evalboard to provide an…
How Bad is TCP? (And What Are the Alternatives?)
Presentation at SNIA Storage Developers Conference, Fremont, CA, Sept. 18-21, 2023 Tail latencies in networking tend to worry us all, whether we implement distributed storage and compute or whether we…
Advantages of Using TCP for GigE Vision Devices
Allied Vision Technologies GmbH in Stadtroda, Germany, has worked with Missing Link Electronics (MLE) to integrate and to optimize MLE NPAP, the TCP/UDP/IP Full Accelerator Stack from Fraunhofer HHI, into…
MLE Updates TCP/UDP/IP Network Protocol Accelerator Platform
MLE has updated NPAP, the Network Protocol Accelerator Platform based on Fraunhofer HHI’s TCP/UDP/IP stack for ASIC and FPGA. Work includes enhancements for performance and interoperability when connecting to Microsoft…
Platform Choices for FPGA-Based In-Network Compute Acceleration
Presentation at SmartNICsSummit 2022, April 26-28, 2022 FPGA-based SmartNICs can provide significant benefits by offloading network data processing off of CPU cores, data-in-motion processing, effectively enabling In-Network Compute. However, FPGA…
MLE NPAC-40G Now Runs CORUNDUM System Stack
MLE has ported and tested a full system stack based on CORUNDUM for NPAC-KETCH, CORUNDUM is a vendor-neutral open source high-performance FPGA-based SmartNIC development platform. NPAC-KETCH is a FHHL PCIe…
MLE NPAC-40G – A Cost-Efficient PCIe SmartNIC Solution
MLE has partnered with Fraunhofer HHI and Elemaster Germany to provide the industry-proven TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) in form of NPAC-40G, a PCIe Network Protocol Accelerator Card. NPAC-40G…
MLE Releases NPAP TCP/UDP/IP Stack Version 1.8.0
MLE has released Version 1.8.0 of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. Changes include fixes for UDP, padding for Ethernet frames smaller than 60 Bytes and an increase…
NPAP RTL Simulation Demonstrates Low-Latency TCP/IP
MLE has complemented NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI, with an RTL Simulation environment for Xilinx Vivado ISim and for the Questa Advanced Simulator from Siemens EDA. This…
MLE & Intel PSG Optimize NPAP for Intel HyperFlex Architecture
As the outcome of joint engineering collaboration between Intel PSG and MLE Germany, an new version of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI was released by MLE. This…