The FPGA Conference Europe 2025 will be held July 1-3 in Munich, Germany. There, MLE will present “FPGA-Based Highly Configurable and Low-Latency Multi GMSL Camera 10GbE RTP Streaming: Performance and Design Choices.”
In the decade of high-performance networking and computing, FPGAs have arisen as a promising and highly convenient solution, offering flexibility, reprogramming capacity and parallelism options. The role of high-performance solutions that offer a high throughput in network-related operations is extremely beneficial in real-time processing tasks executed on embedded systems, such as real-time video streaming.
This presentation showcases the capabilities and obtained performance of our FPGA-based high-speed multi GMSL camera to RTP streaming solution using a single 10GbE link. There will be a walk through the multi GMSL Ser/Des integration, and the FPGA-powered components overview: the CSI-2 to RTP streams translation and the multi-GMSL camera synchronization, accompanied by the highly configurable and low-latency UDP/IP network accelerator. The described high-performance data path is integrated with the on-chip CPU subsystem to provide time synchronization via PTPv2 and enable control and monitoring of the device via the network. At the end of the presentation, we emphasize the most important design choices to build such a multi-camera streaming system. We finally draw the conclusions and the lessons learned from that successful experience.
Date: Thursday July 3rd, 2025
Track 2 – Embedded / Vision (starts at 1:30pm CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join MLE and Analog Devices at FPGA Conference 2025 to discover how we built the highly configurable and low-latency Multi GMSL Camera for 10GbE RTP Streaming!
Enter the promo code FPGA25-CON-MEETME to get 20% discount on all tickets!