Request Support for Xilinx XAUI/RXAUI

Xilinx XAUI/RXAUI

 

May 2020, Xilinx handed over to MLE support for the XAUI and RXAUI IP Cores.

MLE has been supporting customer projects instantiating these IP Cores and is proud to take over the support.

Applications

XAUI

The Xilinx XAUI (eXtended Attachment Unit Interface) IP Core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system.

The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the UltraScaleTM architecture  (GTHE3 transceivers), Zynq®-7000 All Programmable SoC, and 7-series devices.


RXAUI

The Xilinx LogiCORE IP RXAUI core is a high-performance, low pin count 10 Gb/s interface intended to allow physical separation between the data-link layer and physical layer devices in a 10 Gb/s Ethernet system.

The RXAUI core implements a single-speed full-duplex 10 Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx® 7 series FPGAs and UltraScale architecture (GTHE3 transceivers) that comply with Dune Networks specifications. The 7 series FPGA and UltraScale architecture in combination with the RXAUI core, enable the design of RXAUI-based interconnects whether they are chip-to-chip, over backplanes, or connected to 10 Gb/s optical modules.

Availability

The Xilinx 10 Gigabit Attachment Unit Interface (XAUI) and the Xilinx Reduced 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE™ IP is available for the following FPGA families:

Products Availability Matrix

Datasheets and Documentation

Download the original Xilinx datasheets (archived for you by MLE):

RXAUI v4.3 LogiCORE IP Product Guide PG083 (Oct 5, 2016)

XAUI v12.1 LogiCORE IP Product Guide PG053 (Nov 19, 2014)

Or, visit the XIlinx website:

https://www.xilinx.com/products/intellectual-property/rxaui.html

https://www.xilinx.com/products/intellectual-property/xaui.html