Presentation at FOSDEM’22, February 5-6, 2022
This joint presentation between Alex Forencich, UC San Diego, and Ulrich Langenbach, MLE, provides an introduction to the corundum project, implementing a 100 GbE NIC based on Commercial-off-the-shelf (COTS) FPGA cards, e.g. Xilinx Alveo. The project consists of all necessary RTL components, e.g. PCIe DMA engine, NIC datapath, MAC, PHY and integration of vendor specific IP cores, such as transceivers and PCIe hard-IP cores. In combination with the provided driver and debugging utility the ready-to-experiment state just requires a supported FPGA card + compiler to kick-off playing with the project.