Applications of Agentic AI drive chipmakers to boost network and storage interfaces to many hundred Gbps. However, today’s ASIC and SoC emulation systems still clock below 100 MHz. Thus, emulating a modern 800 Gig Ethernet subsystem results in bloated logic with 8,000 (eight thousand) bit-wide internal busses – which is highly inefficient and slows down time-to-market.
Therefore, MLE has created a “missing link” between so-called Hardware-in-the-Loop (HiL) verification and RTL simulation. Originally designed-for as MLE’s in-house verification methodology, this approach combines:
- off-the-shelf FPGA cards (with over 1,600 Gbps I/O bandwidth),
- MLE accelerator IP for network protocols (TCP / UDP / IPv4),
- MLE accelerator IP for storage protocols (NVMe / PCIe),
- open-source “gateware” and software, and
- state-of-the-art RTL simulators with FLI/PLI.
Emulation now runs At-Speed: One or more FPGA Cards are connected to off-the-shelf servers which stimulate and stress-test the “real-life” behaviour and timing of network and storage protocols in the DUT.
Critical portions of the protocol traffic are recorded in standard formats such as Wireshark. Full design visibility into the inner workings of your chip – if needed even at clock-cycle accuracy – is provided by replaying these recordings in the RTL simulator via “cocotb”, the open source coroutine-based co-simulation testbench environment for verifying VHDL and SystemVerilog RTL using Python https://www.cocotb.org/ .
This shortens your engineering turn-around time in the crucial verification phase towards tape-out and it significantly reduces implementation efforts for a proper testbench. Plus, this gives you a much higher test coverage over time: Such a HiL can process 100 Terabytes of test data within 20 minutes, while an emulator needs more than a week!
Looking for High-Speed Networking/NVMe ASIC or FPGA SoC Design Verification?
