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Heterogeneous Multi-Processing for Software-Defined Multi-Tiered Storage Architectures

Presentation at the SNIA Storage Developers Conference 2017 in Santa Clara, CA.

A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store at 10 GigE line rate utilizing Key-Value-Store and TCP/IP Full Accelerators.

(download slides)


 

PXI Express over IP

Published article in the current edition of www.all-electronics.de.

PXI Express over IP allows the connection of PXI-Modules with existing ethernet networks. It is based on the technology of Fraunhofer HHI for processing TCP/IP via FPGA-logic. With this technology it is possible to transmit PCIe-Transaction-Layer-Packages over TCP/IP. The following implementation shows the proof of concept. 

PXI Express over IP ermöglicht die Verbindung von PXI-Modulen über vorhandene Ethernet-Netze. Basierend auf der Technologie vom Fraunhofer HHI zur Verarbeitung von TCP/IP in FPGA-Logik werden PCIe-Transaction-Layer-Pakete über TCP/IP getunnelt. Eine beispielhafte Implementierung zeigt die Machbarkeit dieses Konzeptes.

Read the full article here.


 

Programming Reconfigurable Devices

Programming Reconfigurable Devices via FPGA Regions & Device Tree Overlays 

A technical presentation given by Dipl.-Ing. Ulrich Langenbach and M.Sc. Stefan Wiehler at FOSDEM 2017.

A User View Benchmark on a Declarative FPGA Reconfiguration Framework.  (download slides)


 

Heterogeneous Architectures for Implementation of High-capacity Hyper-converged Storage Devices

Presentation at the SNIA Storage Developers Conference 2016 in Santa Clara, CA.  

A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store at 10 GigE line rate utilizing Key-Value-Store and TCP/IP Full Accelerators.

(download slides)


 

PCI Express over IP, Accelerated - A Low Latency Fabric for System-of-Systems

Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg

FPGA-based full accelerators enable reliable tunneling of PCI Express of existing LAN. This approach is transparent to the CPU Root Complex and Operating System and can be scaled to match 1/10/25/40 GigE line rates.

(download slides)


 

Designing FPGA-Accelerators for Linux Software Using High-Level Synthesis

Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg

High-Level Synthesis facilitates a new, efficient design methodology to accelerate (legacy) software with FPGA-based hardware accelerators.

(download slides)


 

FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols

Presentation at the DESY MTCA Workshop for Industry and Research in Hamburg

Hardware-acceleration of networking protocol stacks, enabled to be optimized for specific applications and underlying network protocols, going beyond a state-of-the-art TCP/IP Offload Engine (TOE) and reaching userspace latencies faster than 1 microsecond.

(download slides)


 

Langzeitverfügbarkeit mit All-Programmable SoCs

Presentation at the IHK Erfa-Kreis Embedded Systems (German Chamber of Commerce) in Augsburg

Presenting benefits of FPGA technology for controlling bill of materials in industrial use cases.

(download slides)


 

Testkonzepte für FPGA/ASIC-Entwicklung

Presentation at the Test-Engineering-Day in Neu-Ulm 2015

Agile design and testing/verification of FPGA and ASIC hardware components.

(download slides)


 

High-Level Synthesis for FPGA Implementation of Network Protocols

Presentation at the Embedded World Conference 2015

Combining network protocol acceleration technology from Fraunhofer HHI with Vivado HLS for programming Xilinx Zynq All Programmable SoC.

(download slides)