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      Technical Publications

      MLE has been invited to numerous international seminars and webinars to share our experience in FPGA development using advanced PCI Express, TCP/UDP/IP stacks, and low-latency IP-core technologies for network and storage acceleration. Here we share the full technical articles and slides of the up-to-date presentations.

      Zone-Based Automotive Backbones Tunneling PCIe

      Zone-Based Automotive Backbones Tunneling PCIe

      Jun 1, 20213 years ago

      Presentation at PCI-SIG Virtual Developers Conference 2021, May 25-26 The need for more safe and eco-friendly vehicles drives automotive connectivity towards so-called Zone-Based Architectures. Inside those so-called Zone Gateways PCIe…

      PCIe-over-TCP-over-TSN-over-10/25GigE

      PCIe-over-TCP-over-TSN-over-10/25GigE

      Sep 24, 20204 years ago

      Presentation at 4th Workshop “Programmable Processing for the Autonomous / Connected Vehicle”, Sept. 24, 2020 at TH Ulm, Germany ADAS and Autonomous Driving push the migration towards Zone-based architectures, which…

      Security / Trusted Execution Environment and Functional Safety with Zync Ultrascale+ MPSoC / RFSoC

      Security / Trusted Execution Environment and Functional Safety with Zync Ultrascale+ MPSoC / RFSoC

      Jul 17, 20195 years ago

      Presentation at the Workshop Programmable Processing for the Autonomous / Connected Vehicle 2019 in Neu-Ulm The security of Embedded Systems has become a key concern, especially when hacked or tampered…

      Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles

      Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles

      Jun 1, 20195 years ago

      Presentation at PCI-SIG Developers Conference 2019 in Santa Clara, CA Using PCIe Non-Transparent Bridging to connect multiple CPUs/GPUs/SoCs/FPGAs within an automotive ECU. This heterogeneous architecture meets tight Size-Weight-and-Power requirements and…

      Network Protocol Acceleration with CAPI SNAP

      Network Protocol Acceleration with CAPI SNAP

      Oct 4, 20186 years ago

      Presentation at IBM OpenPOWER Summit Europe 2018 in Amsterdam, NL. Addressing Network Protocol Acceleration for IBM OpenPOWER Power8 and Power9 with the Coherent Accelerator Processor Interface (CAPI) Storage, Networking and…

      PCIe Range Extension via Robust, Long Reach Protocol Tunnels

      PCIe Range Extension via Robust, Long Reach Protocol Tunnels

      Jun 1, 20186 years ago

      Presentation at PCI-SIG Developers Conference 2018 in Santa Clara, CA Protocol tunnels based on technology from German Fraunhofer Heinrich-Hertz Institute can extend the reach of PCIe connectivityto build systems-of-systems, for…

      Heterogeneous Multi-Processing for Software-Defined Multi-Tiered Storage Architectures

      Heterogeneous Multi-Processing for Software-Defined Multi-Tiered Storage Architectures

      Sep 15, 20177 years ago

      Presentation at the SNIA Storage Developers Conference 2017 in Santa Clara, CA. A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store…

      PXI Express over IP

      PXI Express over IP

      Mar 7, 20177 years ago

      Published article in the current edition of www.all-electronics.de. PXI Express over IP allows the connection of PXI-Modules with existing ethernet networks. It is based on the technology of Fraunhofer HHI…

      Programming Reconfigurable Devices

      Programming Reconfigurable Devices

      Feb 3, 20177 years ago

      Programming Reconfigurable Devices via FPGA Regions & Device Tree Overlays  A technical presentation given by Dipl.-Ing. Ulrich Langenbach and M.Sc. Stefan Wiehler at FOSDEM 2017. A User View Benchmark on…

      Heterogeneous Architectures for Implementation of High-capacity Hyper-converged Storage Devices

      Heterogeneous Architectures for Implementation of High-capacity Hyper-converged Storage Devices

      Sep 20, 20168 years ago

      Presentation at the SNIA Storage Developers Conference 2016 in Santa Clara, CA.   A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store…