Standardization Group for Embedded Technologies (SGeT) is dedicated to developing, promoting, and marketing open standards for embedded hardware and software, and, recently, has embraced working on the needs for FPGA systems. MLE joins its Harmonized FPGA Module (HFM) Standard Development Team to contribute to the standardization of FPGA and FPGA SoC System-on-Modules, with the goal of lowering the barriers to FPGA adoption and development.
In collaboration with its partner, Trenz Electronics—also a SGeT member—MLE has been accelerating FPGA development by utilizing Trenz’s FPGA SoMs that are pre-integrated with MLE’s IP cores. The establishment of a uniform standard for FPGA and FPGA SoC System-on-Modules will further speed up the transition from prototyping to final design, significantly reducing time to market for FPGA development projects.
MLE has released Version 2.4.1 of its Network Protocol Accelerator Platform (NPAP).
NPAP is the TCP/UDP/IP Full Accelerator from Fraunhofer HHI which enjoys production use in FPGA applications for automotive, industrial, medical, robotics, test & measurement and wired/wireless communications.
Changes include optimizations and fixes mostly for TCP interoperability with other TCP implementations such as Windows 10 Enterprise LTSC.
At SDC 2023 last year, we presented Homa, a new datacenter protocol invented by John Ousterhout at Stanford University. Overall, Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks, but not compatible with TCP API. We were told to come back with answers regarding Homa:
A) Can Homa and TCP co-exist in the same network peacefully?
B) How can Homa be accelerated to become more useful and applicable for networked storage?
In our presentation this year we will provide those answers and new collaboration results.
First, we will show network simulation analysis for traffic comprising Homa and TCP. Because of TCP’s congestion management, both protocols not only can co-exist but also be complemented in order to get the best from both: TCP for data streams plus Homa for (shorter) messages with improved tail-end latencies.
We then look into John’s open source implementation for the Linux Kernel, HomaModule and how this can be combined with another open source project, FPGA NIC Corundum.io, for FPGA acceleration of the Homa protocol.
We present experimental results by applying known concepts of CPU offloading to Homa, especially receive side scaling (RSS), segmentation and large receive offloading. After applying the offloads to a traffic pattern with significant traffic portion of payload chunks, the MTU (maximum transmission unit), both the slowdown and RTT, decreases by 5x. The outcome is a Reliable, Rapid, Request-Response Protocol with benefits in storage networking and potential use for networking GPU clusters.
Date: Monday September 16th, 2024
Session: Storage Networking (starts at 10:35pm PST)
Location: Room Winchester, Hyatt Regency Santa Clara, Santa Clara, CA
AMD’s Donna Best (left) and Rhett Whatcott (right) awarded MLE’s Bob Baker (middle) the AMD 2023 Premier Adaptive Computing Partner of the Year award.
San Jose, CA, June 2024 – At the AMD Premier Partner and ATP Summit 2024 held in San Jose this June, Missing Link Electronics (MLE) was honored with the Premier Adaptive Computing Partner of the Year award for the EMEA region. This recognition highlights MLE’s outstanding contributions and unwavering commitment to advancing AMD FPGA technology across various industries and applications.
Since becoming a member of the AMD Partner Program in 2011, MLE has played an essential role in driving the adoption and integration of AMD’s cutting-edge FPGA technology. MLE has leveraged its expertise to promote AMD’s Alveo technology, particularly the Alveo U55 and Alveo V80, through its involvement in key customer engagements for data recording for high-speed cameras.
MLE’s deep understanding of FPGA computing has allowed it to position AMD’s Alveo technology as a cornerstone for high-performance applications. The company’s strategic initiatives and technical acumen have made Alveo technology more accessible and attractive to more customers, thereby enhancing its adoption and integration into various sophisticated systems.
AMD recognizes MLE’s current contributions to the Alveo U55 and V80 as a catalyst for future engagements, broadening the customer base and enhancing the technology’s growth potential.
In their nomination statement, AMD highlighted:
Missing Link Electronics’ dedication to promoting innovative technologies across various applications continues to be vital, and their valuable contributions to the field make them deserving of recognition and this award.
This accolade from AMD not only acknowledges MLE’s past achievements but also underscores the potential for future collaborations and innovations. As the demand for high speed networking and storage grows, MLE is well-positioned to continue its leadership in the field, driving further advancements and expanding the reach of AMD’s technology.
MLE’s commitment to excellence is reflected in its ongoing projects and future plans. We are constantly exploring new FPGA technologies to ensure users to efficiently adopt AMD FPGAs. Our ability to adapt and meet changing market needs has made it a valued partner of AMD and a key player in the technology space.
Berlin 6G Conference is the annual networking event of the German 6G Program, organized by the 6G Platform Germany, will take place at the Berlin Congress Center (BCC) from July 2-4, 2024.
The 6G Platform Germany is an R&D initiative with a total funding of €700 million. One of the core topics is the combination of a secure radio and sensing, so-called Integrated Communication and Sensing (ICAS) with aims to develop such a combination for communication and sensing of the environment and to integrate it into a joint system for the future mobile radio standard 6G.
MLE has been actively contributing to the 6G-ICAS4Mobility project in respect of high-accuracy networking technology with precision time synchronization.
Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.
This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.
Date: Tuesday July 2th, 2024
Track 1 – Application (starts at 4:30pm CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join us at FPGA Conference 2024 to learn more details about the high-speed 400GBit/s data recording technology!
White Rabbit is a technology that allows to synchronize networked devices or endpoints tens of kilometers apart with a sub-nanosecond accuracy. With minor, but incompatible changes, it is now fully integrated into the IEEE1588-2019 or PTP v2.1 standard as high accuracy (HA) profile.
Each endpoint employs frequency and phase measurement and adjustment techniques using field programmable gate arrays (FPGAs) and external voltage-controlled crystal oscillators (VCXOs). This usually requires external circuit boards with specific components not available on commercially off-the-shelf (COTS) development boards.
At the workshop, we will share our results of implementing White Rabbit nodes on multiple development boards, e.g. AMD ZC706 and ZCU102 by only using the FPGA’s resources such as either Mixed-Mode Clock Managers (MMCMs) on the ZC706 or Quad Phase-Locked-Loops (QPLL) on the ZCU102, capable of fully synchronizing with other White Rabbit hardware, such as a Seven Solutions White Rabbit switch (WRS 3/18).
We also compared our synchronized endpoints on the ZCU102 and ZC706 to the timing source of the White Rabbit switch. We obtained initial experimental results of our two VCXO-less White Rabbit implementations using a time interval counter (TIC) for measuring the generated pulse-per-second (PPS) signal and a custom Digital Dual Mixer Time Difference (D-DMTD) circuit for the 10 MHz signal. To validate our measurement approach, we also did a spectrum analysis and a time-interval error analysis of the 10 MHz signals with a professional Rohde&Schwarz RTO1044 oscilloscope.
This update is fixing minor issues with AXI4 bus scheduler fairness, IP Core packaging for AMD/Xilinx Versal FPGA as well as UDP only instantiations. All licensees who are on an active maintenance contract with MLE will have access to this update.
We suggest that customers who are in a late phase of an FPGA design project integrating MLE NPAP shall contact MLE to discuss risks and benefits when updating.
Our FPGA Full System Stacks have a particular focus on high-speed connectivity using PCI Express, MIPI CSI-2, GMSL, Multi-Gigabit Ethernet. We target applications which require reliable, low-latency, high-throughput network transports, high-speed data acquisition, augmented stereo computer vision, high-speed data record & replay. All those are driven by AI algorithms processing massive data from high-resolution cameras, Radar and Lidar sensors.
Please visit us to experience the featured solutions built on top of the latest Trenz SoMs:
We also invite you to join the Embedded World Conference where our engineers present FPGA technology for embedded networking acceleration for high-speed data streaming:
