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      John Ousterhout: “TCP is Dead!” at AI Engineer World’s Fair

      John Ousterhout, Stanford Professor and author of “A Philosophy of Software Design”, turns our attention to the evolving nature of AI networking workloads and why traditional protocols like TCP and RDMA are becoming bottlenecks in modern data center environments!

      The Shift in Workloads

      Historical context:

      AI traffic was dominated by massive, long-running transfers (gigabytes of gradients), where throughput was the primary metric.

      Modern AI:

      Workloads, especially inference and agentic applications, now rely on frequent, small coordination messages (e.g., KV cache lookups, barrier synchronization). These small messages are highly sensitive to latency. The Bottleneck: When small synchronization messages are mixed with large traffic, they get trapped in queues (caused by incast), significantly increasing 99th percentile (tail) latency. This causes GPUs to sit idle, wasting expensive compute resources.

      Why Legacy Protocols Struggle:

      Sender-Driven Congestion Control: TCP and RDMA rely on the sender to detect congestion, often via packet drops or delayed signals from switches. This process is inherently reactive and oscillates, leading to unstable performance.

      Byte Stream Model:

      These protocols view data as an opaque stream of bytes rather than discrete messages, making it difficult to prioritize short, critical tasks.

      The Homa Solution

      John introduces Homa, a clean-slate transport protocol designed for data centers:

      Message-Based:

      Unlike byte streams, Homa understands message boundaries, allowing it to predict traffic and prioritize short messages using Shortest Remaining Processing Time (SRPT).

      Receiver-Driven:

      The receiver controls the flow by issuing grants to senders, effectively managing congestion before it occurs at the switch.

      Priority Queues:

      Homa leverages the multiple hardware queues already present in modern switches to bypass long, queued traffic with low-latency short messages.

      Performance Results:

      Benchmarks show Homa can reduce tail latency for short messages by over 10x compared to TCP, while simultaneously improving performance for large messages.

      Learn More about HOMA Technology?

      MLE NPAP Network Accelerators Now Supports Trenz TE0955 with AMD Versal™ Adaptive SoCs for Physical AI Connectivity

      MLE NPAP Network Accelerators Now Supports The Trenz TE0955 with AMD Versal Adaptive SoCs for Physical AI Connectivity

      Your AI models are ready for prime time, but legacy bus architectures and software-based protocol stacks are choking your system with millisecond lag and heavy CPU overhead?

      In industrial control automation, software stacks simply cannot keep pace with arrays of high-bandwidth sensors arrays.

      Use MLE NPAP TCP/UDP/IPv4 Accelerators on AMD Versal Adaptive SoCs like Trenz TE0955 Starter Kit for reliable ultra-low-latency, high-speed camera connect to your Physical AI.

      By accelerating these slow software protocol stacks, MLE replaces complex data-in-motion bottlenecks with our deterministic, ultra-low-latency hardware pipelines where latency and jitters are measured in nanoseconds.

      MLE NPAP on Trenz TE0955 with AMD Versal™ AI Edge VE2302 supports 1 / 2.5 / 5 / 10 / 25 / 40 / 50 / 100 Gigabit Ethernet to provide a reliable high-bandwidth cameras or sensors for Physical AI Connectivity.

      Trenz TE0955 with AMD Versal™ AI Edge VE2302

      Learn more on how we achieve high-speed camera connectivity with Physical AI:

      Meet MLE at 2026 AMD Embedded Computing Summit in Frankfurt

      AMD Embedded Computing Summit 2026

      The Embedded Computing Summit 2026 will be held October 1 in Wiesbaden, Germany. MLE will be together with Partner Trenz Electronic showcasing FPGA Full System Stacks with AMD Versal.

      The Embedded Computing Summit (ECS) Global Technical Tour from AMD brings together engineers, architects, and technology leaders who are building the next generation of embedded systems.

      Visit us at the ECS to learn more about how our FPGA Full System Stacks accelerate your design projects via using:

      Trenz FPGA Full System Stack composition for AMD Versal

      Date: 01 October, 2026 | 08:00-18:30

      Location: RheinMain Congress Center, Wiesbaden

      AVL Uses MLE’s NVMe Fast FPGA RAID (NVMe FFRAID) for Automotive Data Recording

      AVL List_logo

      NVMe Fast FPGA RAID (NVMe FFRAID) from Missing Link Electronics finds yet another application: AVL List uses this subsystem for accelerated data recording directly from the FPGA’s Programmable Logic (PL) to/from a Non-Volatile Memory Express (NVMe) Solid-State Drive (SSD).

      Looking for High-Speed Data Recording Solution for Automotive Applications?

      AVL List_logo

      AVL List GmbH (“AVL”), headquartered in Graz, Austria, is one of the world’s leading
      mobility technology companies for engineering, simulation, and testing in the
      automotive industry, and in other sectors such as aviation, marine, and energy. Its
      customers include leading automotive manufacturers, suppliers, and companies from
      the energy, transport, and industrial sectors.

      For more than a decade MLE has demonstrated expertise in offloading CPUs and in
      accelerating software-rich system stacks via so-called Domain-Specific Architectures. To
      implement this MLE makes heavy use of heterogeneous processing such as FPGAs
      which are programmed using C++/C/SystemC as well as VHDL and Verilog HDL for FPGA
      design. MLE is headquartered in Silicon Valley with offices in Berlin and Neu-Ulm
      Germany.

      MLE Presents “Real-Time Networking with Stanford’s HOMA Protocol” at Storage Developers Conference 2026

      SNIA Developer Conference_2026

      The Storage Developers Conference (SDC) 2026 of SNIA, the Storage and Networking Industry Alliance, will be held Sept. 28-30 in Santa Clara, CA. There, MLE will present “Real-Time Networking with Stanford’s HOMA Protocol“.

      At SDC 2023 and SDC 2024, we presented Homa, a reliable datacenter transport-layer protocol invented by John Ousterhout at Stanford University. We were able to demonstrate that Homa and TCP can co-exist in the same network “peacefully”, and how Homa can be accelerated by something similar to what Offload Engines do for TCP.

      Today, (almost) everybody’s eyes are on datacenter infrastructure and AI clusters because of the challenging Terabit line rates and the high volume numbers of network ports. Nevertheless, there are many other applications which can also benefit from Homa: 

      • Systems-of-systems such as zone-based automotive networks
      • Telecommunication core networks
      • Converged IT/OT networks in industrial automation
      • Backbones in humanoid robots
      • Sensor Open Systems Architectures in aerospace & defense

      These systems need a reliable transport-layer protocol which minimizes tail latency and optimizes infrastructure efficiency to deliver bandwidths of 10 Gbps, and more.

      Many of these systems require hard real-time behavior which – in theory – matches with Homa’s attributes of being:

      1. message-based
      2. connection-less
      3. using receiver-driven congestion control
      4. run-to-completion (SRPT)

      Time Sensitive Networking (TSN) has become the de-facto choice using IEEE standard Ethernet. TSN comes with time-synchronization, traffic shaping, reliability and resource management and works well with higher-layer protocols such as TCP.

      Hence, in our presentation this year we will share insights on how Homa can be run over TSN and, in particular, the effects of different forms of traffic shaping on Homa’s core functions. We plan to start with a refresher on Homa and then dive into architecture choices when running TSN and multiple Gbps. This is complemented by presenting “Light Rabbit” which is a cost-optimized variant of CERN’s White Rabbit high-accuracy time synchronization which utilizes programmability of modern PLLs for frequency and phase synchronization to achieve nano-second accuracy. We close by presenting first experimental results of running Homa over TSN to achieve the best of both worlds.

      Date: September 28-30, 2026

      Location: Hyatt Regency Santa Clara, Santa Clara, CA

      MLE Presents “Beyond the Bitstream: Streamlining Heterogeneous Computing with the MLE FPGA Full System Stack” at FPGA Conference 2026

      Beyond the Bitstream: Streamlining Heterogeneous Computing with the MLE FPGA Full System Stack - FPGA Conference 2026

      The FPGA Conference Europe 2026 will be held June 30 – July 2 in Munich, Germany. There,  MLE will present “Beyond the Bitstream: Streamlining Heterogeneous Computing with the MLE FPGA Full System Stack.”

      As the demand for domain-specific architectures grows, FPGAs have become essential for offloading compute-intensive tasks in networking, storage, and automotive sectors. However, the “Integration Gap”—the months of engineering effort required to build reliable PCIe/DMA infrastructure, kernel drivers, and memory management—often acts as a barrier to entry.

      This presentation introduces the Missing Link Electronics (MLE) FPGA Full System Stack (FFSS), a pre-validated, cross-platform framework designed to eliminate architectural “plumbing” and accelerate application-specific development.

      Date: Thursday July 2rd, 2026

      Track Architecture 2:20pm-3:00pm CEST

      Location: Hotel NH München East Conference Center, Munich, Germany

      Join MLE at FPGA Conference 2026 and discover how our FPGA Full System Stacks de-risk design process, rapidly validate your prototypes, and accelerate your time-to-market!

      Alpha Data and MLE Partner To Cut Firmware Development Burden From Defense FPGA Procurement

      Alpha Data SOSA-aligned FPGA Full System Stacks

      Littleton, CO, June 8, 2026 – Alpha Data Parallel Systems and Missing Link Electronics (MLE) have announced a technology partnership aimed at simplifying FPGA (Field-Programmable Gate Array) deployment for defense and aerospace customers.

      The collaboration introduces a new concept “FPGA Full System Stacks”, integrated hardware and software platforms designed to reduce procurement complexity, development risk, and time-to-deployment for FPGA based systems.

      The platforms combine Alpha Data’s ruggedized, SOSA (Sensor Open Systems Architecture)-aligned FPGA hardware with MLE’s pre-validated IP cores and software stacks, covering applications including high-speed data recording, signal processing, data transport, and system-level firmware. The result is a fully integrated FPGA platform delivered through a single vendor relationship.

      Defense programs often face delays and complexity when procuring FPGA software and specialist IP separately from hardware. The FPGA Full System Stack approach allows customers to source integrated hardware and software through a single approved supplier. Because each platform is validated end-to-end before delivery, customers can reduce qualification overhead, accelerate development timelines, and lower integration risk. 

      As AMD Premier Partners, both companies bring extensive FPGA expertise to the offering. The collaboration provides customers with a single point of accountability across hardware, software, and overall system performance.

      Adam Smith, Chief Executive Officer of Alpha Data, said:

      “Defense customers should not have to carry the cost and risk of integrating hardware and software themselves. By partnering with MLE, we’re lifting the procurement burden from our end customers, offering hardware and software that is qualified and procured together, ready to deploy. That is a meaningful change for program teams working under time and budget pressure.”

      Endric Schubert, CTO of Missing Link Electronics added:

      “The new Alpha Data FPGA Full System Stacks integrates and verifies everything engineers need to develop their application immediately. This eliminates the time and effort required to build a prototype from scratch, enabling teams to validate concepts rapidly. At the same time, this integrated approach ensures the users are fully supported by both hardware and software experts throughout their development cycle.”

      The offering targets mission-critical aerospace and defense applications including, radar and sonar systems, electromagnetic spectrum operations (EMSO), military communications using MIMO and pre-6G waveform processing, edge AI inference, and signals intelligence (SIGINT).

      The product line also supports space and satellite applications, including hardware configurations with single-event latch-up mitigation for high-radiation environments. Each platform is SOSA-aligned and qualified for deployment in ruggedized, conduction-cooled environments.

      Alpha Data SOSA-aligned FPGA Full System Stack in VPX format

      FFSS-ADA-VA330 VPX module with PS or PL-based NVMe data streaming

      FFSS-ADA-VA330 3U VPX Module

      • Based on AMD Versal™ RF VR1602 (VSVA2488) SoC
      • 4x 32GByte LPDDR5 SDRAM
      • High-speed NVMe SSD Connectivity to/from FPGA Programmable Logic, configured and wired to M.2 Connector
        • Up to 5 GiB/s read/write speeds (depend on SSD)
        • 551k LUTs total (approx. 30k LUTs reserved by FFSS)
      • Support Data Generator and Data Checker test application (use as design example)
      • Support Data Recording & Replay
      FFSS-ADA-V9202 VPX Module

      FFSS-ADA-V9202 3U VPX Module

      • Based on AMD Zynq® Ultrascale+ XCZU47DR-2, XCZU48DR-2 (FFVE1156)
      • 1x 16Gb DDR4 SDRAM (32-bit wide to PS) and 2x 8Gb DDR4 SDRAM (8-bit wide to PL)
      • High-speed NVMe SSD Connectivity to/from FPGA Programmable Logic
        • Up to 5 GiB/s read/write speeds (depend on SSD)
        • 425k LUTs total (approx. 30k LUTs reserved by FFSS)
      • Support Data Generator and Data Checker test application (use as design example)
      • Support Data Recording & Replay

      Looking for NVMe Stacks Integrated SOSA-aligned VPX Modules?

      Strengthening Edge Trust with Hardware-Backed OP-TEE Integration

      Advanced Hardware-Accelerated OP-TEE Security on AMD Versal FPGAs

      Securing data at the edge requires close alignment between hardware capabilities and trusted software environments. Missing Link Electronics (MLE) has extended the Open Portable Trusted Execution Environment (OP-TEE) to support advanced hardware-accelerated cryptographic capabilities on a high-performance AMD Versal™ Adaptive SoC platform.

      This work focuses on integrating key cryptographic primitives directly into the trusted execution environment, enabling efficient and secure access to hardware-backed security features. The implementation includes support for:

      • SHA2-256, SHA2-384, and SHA2-512 hashing
      • Counter DRBG (Deterministic Random Bit Generator)
      • ECDSA Key Generation, Signature Generation, and Verification

      By tightly coupling OP-TEE with on-chip cryptographic accelerators, the solution enables high-assurance execution environments suitable for security-sensitive edge deployments.

      As a key milestone, the implementation achieved validation through the NIST Cryptographic Algorithm Validation Program (CAVP), demonstrating compliance with established federal cryptographic standards.

      This work highlights MLE’s capability to deliver secure, hardware-integrated trusted execution environments that support the growing complexity of edge computing systems.

      Looking for Hardware-Accelerated OP-TEE Solution for Data Security?

      High-Precision Synchronization for 77GHz Radar Networks via White Rabbit Technology

      High-Precision Synchronization for 77GHz Radar Networks via White Rabbit

      As autonomous driving and advanced driver-assistance systems (ADAS) evolve, modern vehicles require unprecedented levels of environmental awareness to enhance and ensure driving safety. According to the article “High-Precision Synchronization for 77-GHz Radar Networks via White Rabbit” in Journal of IEEE Transactions on Radar Systems, this demand is driving the deployment of distributed 77GHz automotive radar networks, which rely on coherent data processing to create a precise, real-time map of the vehicle’s surroundings. To achieve this, the distributed sensors must be synchronized with sub-nanosecond accuracy. Existing wired synchronization methods, however, incur high cabling costs and present challenges in complexity and scalability.

      White Rabbit (WR) Technology, an Ethernet-based technology providing sub-nanosecond accuracy, enables simultaneous synchronization and data transfer over a standard Ethernet link, thus eliminating the need for a dedicated custom clock distribution network. To implement this technology in FPGAs, it typically requires external voltage-controlled crystal oscillators (VCXOs) for measurement and adjustment. However, such components are often missing on commercially off-the-shelf (COTS) development boards. This forces interested developers to invest inexpensive, specialized hardware just to get started with White Rabbit technology.

      MLE supports White Rabbit Technology development in CERN’s White Rabbit Project and provides Dormouse White Rabbit FPGA Mezzanine Card (FMC) to complement (or replace) expensive VCXOs and trade-off BoM cost vs. minor loss of accuracy by using modern on-chip PLL for phase-shifting.

      The Dormouse White Rabbit FPGA FMC features tunable oscillators that are required to deploy and operate White Rabbit, an open-source FPGA-based implementation of Precision Time Protocol 2.1 (PTP v2.1), and provides capabilities to generate LF and RF reference clocks derived from a White Rabbit network. For these tasks a high performance OCXO (DOT050V), two programmable and tunable oscillators (SiT3521, Si549) and a flexible PLL (HMC7044) are available for use on the card.

      With the Dormouse White Rabbit FPGA FMC, White Rabbit implementation can achieve < 1 ns accuracy and < 100 ps precision of the PTP v2.1 high-accuracy profile for building a time and frequency distributed 77GHz automotive radar networks.

      MLE Dormouse FMC_Front

      Features of Dormouse White Rabbit FMC:

      The MLE Dormouse White Rabbit FMC is now available on our partner Trenz’s online shop.

      Implementing Sub-Nanosecond Synchronization for a Distributed Automotive Radar Networks?