Missing Link Electronics (MLE) has released update V1.4.9 for the network acceleration technology from German Fraunhofer Heinrich-Hertz-Institute. Changes include various fixes for corner cases and to enhance support for the Xilinx 10G/25G PCS/PMA subsystem. This brings full TCP/UDP/IP connectivity for 10/25/40/50 Gigabit Ethernet to FPGAs by offloading protocol processing into programmable logic.
Missing Link Electronics (MLE) has partnered with Trenz Electronic to deliver FPGA-based turnkey solutions integrating FPGA and SoC modules manufactured by Trenz and IP Cores and Subsystems from MLE.
The Xilinx Alliance Partner Program, a worldwide ecosystem of qualified companies who offer Acceleration solutions, IP cores, Design Services, and Board development & production, features Missing Link Electronics professional services for Security. The services are built on-top of a strong foundation using Xilinx Zynq UltraScale+ MPSoC and Xilinx Zynq UltraScale+ RFSoC Hardware Root-of-Trust and open source ARM Secure OP-TEE.
MLE will support researchers in using the Intel Programmable Accelerator Cards (PAC) D5005 installed in the new High-Performance Cluster JUSTUS 2 at Ulm University in Germany. As an Intel FPGA Design Solutions Partner MLE has been given access to FPGA design tools and design methodologies including Intel oneAPI Data Parallel C++ and and will actively work with the KIZ at Ulm University so researches see maximum results from FPGA acceleration.
From Tuesday to Thursday, February 25-27, 2020, MLE will exhibit at Embedded World Conference 2020 in Nuremberg, Germany. For expert discussions on FPGA-based architectures for automotive, industrial and other embedded systems please visit MLE in Hall 3A Booth 331.
With great support from the Intel PSG Team Europe, MLE has ported the 10/25 Gigabit Ethernet Network Protocol Acceleration Platform (NPAP) based on the TCP/UDP/IP Network Protocol Accelerator from Fraunhofer Heinrich-Hertz-Institute Berlin, Germany, to Intel’s Stratix 10 Device Family. This lays the necessary foundation to perform TCP/UDP/IP protocol full acceleration for users of Intel’s new Stratix 10 based FPGA Programmable Accelerator Cards (PAC) D-5005.
Following a successful review by the Xilinx Security Center-of-Excellence, MLE now releases the OP-TEE Free Open-Source Edition for the Zynq UltraScale+ MPSoC and RFSoC devices from Xilinx (ZynqMP). OP-TEE is an open-source project under the Linaro Security Working Group (SWG) for the ARM Trusted Execution Environment (TEE). Team MLE volunteered and took responsibility for maintaining functions specific to ZynqMP. Read more information on MLE’s offerings for Security and Trust. OP-TEE can be downloaded at www.github.com/OP-TEE/
The automated Vivado Build System, open-sourced by MLE to increase FPGA design productivity, is featured in the Xilinx Blog. This collection of scripts facilitates Continuous Integration (CI), and ensures fully reproducible results later in the development and product lifecycle.
MLE releases NVMe Streamer which is a so-called Full Accelerator NVMe host subsystem integrated into FPGAs. NVMe Streamer offloads the NVMe protocol into programmable logic and enables to stream data from FPGA blocks in and out of directly-attached NVMe SSDs.