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      Zone-Based Automotive Backbones Tunneling PCIe

      Missing Link Electronics (MLE) announced today that they are partnering with Fraunhofer Heinrich-Hertz-Institute (HHI) and Fraunhofer Institute for Photonic Microsystems (IPMS) on ultra-reliable, deterministic low-latency transports for automotive networks tunneling PCI Express® (PCIe®) architecture.

      The need for more safe and eco-friendly vehicles drives automotive connectivity towards so-called Zone-Based Architectures. Inside those so-called Zone Gateways PCIe technology provides the connectivity between multiple System-on-Chip (SoC), CPUs, GPUs, and FPGAs for scalable performance. Within the automotive network, multiple Zone Gateways connect with each other via the emerging IEEE standards “Time Sensitive Networking” (TSN).

      Today, Fraunhofer and MLE can provide a working proof-of-concept in form of a digital circuit & system stack which encapsulates and decapsulates PCIe packets (and other protocols) over real-time automotive TSN Ethernet and which scales up to 100 Gbps.

      “When we started working on network protocol acceleration in 2010 we looked at future connectivity needs for systems-of-systems such as ships and cars”, states Ulrich Langenbach, formerly with Fraunhofer HHI and now Director Engineering at MLE. “Therefore, our approach does address key topology requirements for modern vehicles which is reliable and cost-efficient PCIe long-range, support for NVMe SSD storage, as well as CPU-to-CPU communication via PCIe Non-Transparent Bridges (NTB)”.

      “Our approach of closely adhering to the OSI Layers makes our TSN Switched-Endpoint very interoperable with different Ethernet PHY solutions”, says Marcus Pietzsch, Group Leader IP Cores and ASIC Design at IPMS and emphasizes: “This is vital as the standards and commercial offerings for TSN and for automotive Ethernet are still very fluid!”

      “PCI-SIG’s mission is to bring together developers seeking innovation and product compliance around current and future PCIe specifications,” said PCI-SIG President Al Yanes. “The purpose of PCI-SIG’s Automotive Work Group is to facilitate the discussion of PCIe technology in the automotive ecosystem with member companies like MLE.”

      Algoblu partners with MLE on FPGA-Based Network Element Virtualization

      Algoblu announced today its Network Element Virtualization (NEV) platform that virtualizes and orchestrates underlying network resources to help carriers offer more application-oriented customized services to both commercial and residential customers. Thanks to the new FPGA-based technology, the cost per bit decreases by more than four times and operation efficiency increases three times.

      “We are pleased to collaborate with Algoblu to develop a Network Element Virtualization chip built on leading-edge FPGA technology. The chip is key to Algoblu’s NEV architecture with an FPGA-based SMartNIC, all developed in an elegant way,” says Dr. Endric Schubert, CTO at Missing Link Electronics.

       

      MLE joins PCI-SIG Automotive Workgroup

      PCI Express (PCIe) has significant advantages which help to drive innovation towards more eco-friendly and safer vehicles. MLE is a member of PCI-SIG and has been providing technology and solutions for PCIe-based Long-Range Tunneling used for automotive backbone connectivity and is proud to volunteer for PCI-SIG's newly formed Automotive Workgroup.

       

      Deterministic Networking with TSN-10/25/50/100G

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      MLE presents “Deterministic Networking with TCP-TSN-Cores for 10/25/50/100 Gigabit Ethernet” in Technical Brief MLE-TB20201203.

      We all observe a growing need to connect computers with each other with shorter delays (i.e. lower latencies) and higher bandwidth, in particular for High-Performance Computing (HPC) in the data center and in embedded systems such as advanced industrial robotics or autonomous vehicles, requiring the so-called deterministic networking. Processing of TCP/IP based network protocols at speeds of 10 Gbps and beyond demand kernel bypass solutions (such as Intel’s DPDK or Solarflare’s/Xilinx’ Onload or Mellanox/NVida VMA) and/or so-called TOEs (TCP Offload Engines). 

      Domain-Specific Architectures (DSA) use so-called heterogeneous computing elements, also known as Cores with the objective to put the compute burden where it belongs. This is a well established approach going back to the early days when an x86 CPU was partnered with an x87 for better floating-point processing. Today, it is common to deploy various flavors of Cores, for example:

      • DSP Cores for digital signal processing in telecommunications
      • Shader Cores optimized for image processing, as they can be found in modern Graphics Processing Units (GPU) 
      • Tensor Processing Units (TPU) Cores which are optimized for Artificial Intelligence and Deep Learning

      This is because such (special purpose) fixed-function or programmable function accelerator Cores are optimized for a particular domain and, when properly used, not only take processing load off the (general purpose) CPU but also deliver better overall performance (which is data processed per time) and better efficiency (which is performance per Watt).

      Over the following pages we will make a case for processing TCP/IP over TSN over 10/25/50/100 Gigabit Ethernet on dedicated Cores which has significant advantages in particular for real-time Ethernet and Deterministic Networking. These so-called TCP-TSN-Cores can be integrated either in FPGAs or in SoCs (ASIC and ASSP). As we will show, TCP-TSN-Cores are more than just a TOE – the commonly used approach for network protocol acceleration. By running the entire network protocol stack from OSI Layer 2 to at least Layer 4 in a dedicated integrated circuit – a so-called Full Accelerator – we can remove (general purpose) CPUs entirely from the datapath. 

      Hence, TCP-TSN-Cores can deliver very low bounded and deterministic latency with predictable scalability needed for 10/25/50/100 Gigabit Deterministic Networking. 

      Read Technical Brief