NPAP is the TCP/UDP/IP Full Accelerator from Fraunhofer HHI which enjoys production use in FPGA applications for automotive, industrial, medical, robotics, test & measurement and wired/wireless communications.
Newly introduced features include built-in diagnostics plus functionality to emulate Network Impairment.
Also added was support for the new Agilex 5E FPGA devices from Altera where MLE NPAP integrates with the GTS Ethernet Intel® FPGA Hard IP.
PCO, an Excelitas Technologies® Corp. brand, is a leading specialist and Pioneer in Cameras and Optoelectronics with more than 30 years of expert knowledge and experience of developing and manufacturing high-end imaging systems. The company’s cutting edge sCMOS and high-speed cameras are used in scientific and industrial research, automotive testing, quality control, metrology and a large variety of other applications all over the world.
PCO has licensed MLE’s FFRAID for use in optimized recording systems that complement PCO’s high-speed cameras.
The recorder is equipped with a high-performance SSD tray, providing fast data storage with a capacity of up to 8 TB. It supports the simultaneous connection of 1 to 8 cameras and features a 25G Ethernet connection for efficient data transfer to a PC. The system offers flexible recording modes, including Record, Pause, Play, and Circular Buffer Recording, ensuring versatile operation for various applications.
At Embedded World 2025 in Nuremberg Exhibition from March 11-13 in Nuremberg, Germany, Analog Devices (ADI: Hall 4A: Stand 360) and Missing Link Electronics (MLE: Hall 5: Stand 140) will be sharing solutions that are redefining high-speed Ethernet connectivity. Together, they are paving the way for the next generation of embedded applications across various markets ranging from automotive to industrial automation to IoT.
Mark your calendar to make a stop at the ADI booth to see the “High-Performance Analog Meets AI” demo. This demo dives into the shift from traditional signal processing to AI-driven flows and speaks to the trend of extracting data from high-performance, high-data-rate analog signal chains for AI model training and real-time inference.
The demo shows how ADI’s data extraction framework, built on top of open-source software, open-source FPGA infrastructure, and scalable host-side data management flows, can be used in conjunction with ADI’s high-performance transceivers and converters to streamline the development and deployment of AI-capable and intelligent edge systems.
MLE helps ADI implement Corundum – an open-source, high-performance FPGA-based NIC and platform – on the ADRV9009-ZU11EG System on Module (see ADRV9009-ZU11EG RF-SOM Hardware Overview). Via Linux NAPI, the standard open source Linux network stack, data is captured in system memory and then streamed to the Nvidia IGX/Host PC for AI processing.
Learn more about how MLE enables high performance analog for AI processing and at ADI’s EZ Blog.
High-performance data extraction architecture for AI model training and real-time inference in high-data-rate analog signal chains
MLE helps ADI implement Corundum on the ADRV9009-ZU11EG System on Module
Auto/TSN enables Software-Defined Vehicles (SDV) and zonal architectures by virtualizing industry-standard automotive such as CAN, LIN, or CSI-2 for transport over in-vehicle network “backbones”.
Auto/RPS is MLE’s FPGA-based Rapid Prototyping System (RPS) catering to the specific needs of automotive engineers designing next-generation Zone Based Architectures. MLE Auto/RPS enables automotive system engineers to design and to validate software-defined vehicle (SDV) functions along with MLE Auto/TSN in-vehicle networking.
MLE Fast FPGA RAID (FFRAID) is a fast and FPGA-based NVMe RAID solution that can transfer bulky data from multiple sensors to a RAID of NVMe SSDs at speeds up to 400 Gbps. The FFRAID implements a channel-based architecture, supports data-in-motion pre- and post-processing and is highly scalable with regards to bandwidth and recording capacity.
Altera, Arrow and MLE have worked together to migrate MQNIC, an FPGA-based Network Interface Card (NIC) from the open source Corundum.io project to Altera Agilex 5E on the Arrow AXE5 Eagle Development Platform.
High Performance Analog Meets AI
📍Hall 1, booth #1-301
Analog Devices and MLE will be sharing solutions that are redefining high-speed Ethernet connectivity. Together, they are paving the way for the next generation of embedded applications across various markets ranging from automotive to industrial automation to IoT.
Lattice and MLE have worked together to migrate MQNIC, an FPGA-based Network Interface Card (NIC) from the open source Corundum.io project to Lattice Avant-G and Avant-X FPGAs on the Lattice Avant-G/X Versa Board.
Accelerated TCP/IP for High-Speed Camera Connectivity
📍Hall 3A, booth #3A-135
NPAP, the TCP/IP Full Accelerator from Fraunhofer HHI, provides TCP connectivity in accordance with the GigE Vision standard. Microchip has worked with MLE to integrate and to optimize MLE NPAP for PolarFire and PolarFire SoC, suitable for next-generation camera products.
Trade Show Information
Date: March 11-13, 2025
Location: Nuremberg Convention Center, Nuremberg, Germany
Booth: Hall 5 #5-140
Visit us at booth #5-140 and talk with our FPGA experts to learn about how to accelerate your industrial network connectivity with a “shift-left approach”!
MLE’s Network Protocol Accelerator Platform (NPAP) runs the entire TCP/UDP/IPv4 protocol stack in a digital circuit, i.e. FPGA or ASIC. This means NPAP must meet some challenging combinations of Your requirements:
First (and most important of all), NPAP must be compatible and fully interoperable with the many TCP/UDP/IP software stacks in use today
Second, users expect outstanding performance: High throughput (close to line rate) and low latency (in form of short Round-Trip Times)
Resource efficiency comes next: This means avoiding “FPGA Bloat” as well as options to tune Rx and Tx buffer sizes
Then, users want us to support leading FPGA vendors and device families with their many different high-speed transceivers and Ethernet subsystems
And last, a clean and affordable license model that makes sense even for low unit volume applications such as in Test & Measurement
Over the years, MLE’s engineering team has invested significantly in NPAP’s test automation. CI (continuous integration) tools such as Gitlab integrating Pytest for simulation and hardware test cases have enabled us to run the TCP/IP stack on many different FPGA boards, to interact with different software stacks such as the many versions in the open source Linux kernel, Microsoft® Windows with its many flavors, kernel bypass implementations such as AMD SolarFlare® Onload or Nvidia® Mellanox Messaging Accelerator (VMA), for example.
One key feature to be FPGA resource efficient is the underlying 128 bit wide dataflow architecture, as this balances throughput, FPGA clock speeds and avoids “FPGA Bloat”. Other features include options for QoS (Quality-of-Service) to prioritize some TCP streams over others and means for asymmetric buffer management.
We have put special focus on cornercases which impact performance, such as Bit Errors on the wire which cause TCP Re-Transmissions which, again, cause the net throughput to drop.
An (optional) Bit Error Insertion module facilitates Your integration and testing for “not so standard” Ethernet links: Over the years we have seen systems using very low power PHYs, multiple slip-rings, “special” connectors, and such, and wanted everything just to work as much as our customers!
Thanks to the great enablement from our FPGA partners, we have always been able to start migration and testing once new FPGA hardware enters the market.
Today, MLE NPAP runs on (almost) all AMD devices starting from 7-series up to Versal (with clear plans for Versal Gen 2), and on many of those AMD Alveo cards, too.
MLE NPAP is regularly tested for Microchip PolarFire because this is important to our customers from the low-power, cost-optimized world of FPGA based cameras and computer vision.
If you have been a licensee of MLE NPAP who is interested in upgrading to the latest latest Version 2.4.3, or if your new project can benefit from reliable TCP/UDP/IP connectivity, please contact your MLE sales representative.
MLE is shipping to the first customers the Dormouse White Rabbit FPGA Mezzanine Card (FMC), specifically designed to implement White Rabbit technology for highly accurate time and frequency distribution Ethernet-based networks.
The Dormouse White Rabbit FPGA FMC features tunable oscillators that are required to deploy and operate White Rabbit, an open-source FPGA-based implementation of Precision Time Protocol 2.1 (PTP v2.1). With the Dormouse White Rabbit FPGA FMC, White Rabbit implementation can achieve sub-nanosecond accuracy of the PTP v2.1 high-accuracy profile, making it an ideal solution for building a time and frequency distribution network for applications like data center, radar, neutrino telescope, automotive, or control systems.
The Dormouse White Rabbit FPGA FMC provides capabilities to generate LF and RF reference clocks derived from a White Rabbit network. For these tasks a high performance OCXO (DOT050V), two programmable and tunable oscillators (SiT3521, Si549) and a flexible PLL (HMC7044) are available for use on the card.
In addition to the clocking infrastructure, an SFP+ interface provides 1 GbE / White Rabbit connectivity, which enables boards that do not provide an SFP+ interface.
Features of White Rabbit High-Accuracy Time Synchronization:
The White Rabbit Project is a multi-laboratory, multi-company and multinational collaboration to develop new technology that provides a versatile solution for control and data acquisition systems. The White Rabbit Network is based on existing IEEE standards while extending these standards in a backward-compatible way if needed to meet CERN‘s requirement.
The Lattice Developers Conference 2024 takes place both virtually and physically in San Jose, CA, on December 10, 2024. Here, MLE presents the Robo/TSN for Industrial Network Virtualization with Multi-Gigabit Ethernet and Multi Protocols.
MLE Robo/TSN is an advanced FPGA-based network virtualization technology designed for multi-Gigabit TSN (Time Sensitive Networking), leveraging open standards to deliver seamless, high-speed connectivity. It integrates access points and SmartNICs to efficiently connect high-speed devices such as sensors, robotic arms, and machinery to datacenter, supporting data transfer rates of up to 100Gbps. Robo/TSN can also virtualize PLCs and run PLC system on datacenter infrastructure with advantages like virtualization, containerization, redundancy, backup organization etc. and without any compromises concerning real-time and high-speed requirements.
Features of MLE Robo/TSN:
Bridging/ Tunneling of several protocols like PCIe, Ethercat, Profinet, Ethernet, CAN, etc.
Scalable from 1 to 100 Gbps
Precision time synchronization with IEEE TSN or IEEE 1588 v2 (CERN White Rabbit)
Hardware accelerated deterministic transport with Ultra Low Latency (RTT < 600 ns)
Reliable transports via TCP/IP and/or Quad-RP/IP
Optional security features MACsec, IPSec, TLS
Learn more about the performance of MLE Robo/TSN solution with Lattice FPGAs at Lattice Developers Conference 2024!
The AMD-Xilinx Security Working Group takes place face-to-face in Munich, Germany, from December 10-11, 2024. Presentations include the latest security features in Versal Gen 2 and other AMD FPGA families, and updates for the product roadmap.
MLE, a Premier AMD Alliance Member, will participate and showcase its latest security solutions and services. These include TCP/IP with TLS (NPAP and TLS) implemented in RTL for high-speed, secure communication, as well as expertise in hardening AMD Versal and AMD Zynq UltraScale+ MPSoC-based systems for use in data center networking, automotive and telecommunications.
MLE is actively contributing to the White Rabbit Project, a group focusing on advancing network synchronization research, to synchronize their beamforming and detector units to achieve the goal of sub-nanosecond synchronization.
White Rabbit delivers sub-nanosecond accuracy in synchronizing networked devices over distances of tens of kilometers. Typically, implementing this technology in FPGAs requires external voltage-controlled crystal oscillators (VCXOs) for measurement and adjustment. However, such components are often missing on commercially off-the-shelf (COTS) development boards. This forces interested developers to invest inexpensive, specialized hardware just to get started with White Rabbit technology.
MLE has overcome this challenge by developing a VCXO-less White Rabbit solution that operates entirely using FPGA resources. This breakthrough enables the deployment of White Rabbit nodes across a range of development boards without the need for external components.
▲ MLE implements VCXO-less White Rabbit solution on AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Board (WR Switch loaned by DESY)
