Programming Reconfigurable Devices via FPGA Regions & Device Tree Overlays
A technical presentation given by Dipl.-Ing. Ulrich Langenbach and M.Sc. Stefan Wiehler at FOSDEM 2017.
A User View Benchmark on a Declarative FPGA Reconfiguration Framework.
A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store at 10 GigE line rate utilizing Key-Value-Store and TCP/IP Full Accelerators.
FPGA-based full accelerators enable reliable tunneling of PCI Express of existing LAN. This approach is transparent to the CPU Root Complex and Operating System and can be scaled to match 1/10/25/40 GigE line rates.
High-Level Synthesis facilitates a new, efficient design methodology to accelerate (legacy) software with FPGA-based hardware accelerators.
Hardware-acceleration of networking protocol stacks, enabled to be optimized for specific applications and underlying network protocols, going beyond a state-of-the-art TCP/IP Offload Engine (TOE) and reaching userspace latencies faster than 1 microsecond.
Presenting benefits of FPGA technology for controlling bill of materials in industrial use cases.
Presentation at the Test-Engineering-Day in Neu-Ulm 2015Agile design and testing/verification of FPGA and ASIC hardware components.
Combining network protocol acceleration technology from Fraunhofer HHI with Vivado HLS for programming Xilinx Zynq All Programmable SoC.
High-Level-Synthesis Design for Xilinx Zynq Accelerators with Vivado HLS (in German).