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      How Bad is TCP? (And What Are the Alternatives?)

      Presentation at SNIA Storage Developers Conference, Fremont, CA, Sept. 18-21, 2023

      Tail latencies in networking tend to worry us all, whether we implement distributed storage and compute or whether we connect systems-of-systems in automotive or factory automation, for example. Same goes for the computational burden of processing networking protocols.

      One of the foundations of reliable networking is TCP, the Transmission Control Protocol which was introduced half a century ago. Today, TCP is ubiquitous: In the data center, in mobile communication, the Internet and in (embedded) systems-of-systems. However, TCP has some significant drawbacks including unpredictable tail latency and a significant computational burden.

      This presentation aims to guide engineers in their systems design by sharing quantitative analysis results and describing alternatives. For latency analysis we present benchmarks results from network simulation which show the significant tail latencies for TCP. We also share benchmark results from running TCP implementations of different Linux kernels – with sometimes surprising outcomes.

      Benchmarks for the computational burden extend our analysis of implementations of TCP processing in various Linux kernels. We discuss a metric for Efficiency as in Throughput per CPU load and compare results.

      Finally, we present Homa from John Ousterhout’s team at Stanford University. Homa is an implementation of a so-called Quad-RP, i.e. Rapid, Reliable Request-Response Protocol: Instead of streams it is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized architectures. It puts the recipients in control which enables proactive approaches to congestion control and thereby achieves better network infrastructure utilization. While not TCP API compatible, overall, Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks.

      We close with an outlook of the potential realizations in ASIC and FPGA to enable energy – efficient, deterministic networking as well as potential use in networked storage.

      Terms-of-Use Policy (June 2023)

      Terms-of-Use Policy (June 2023)

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      Technical Publications

      Technical Publications

      MLE has been invited to numerous international seminars and webinars to share our experience in FPGA development using advanced PCI Express, TCP/UDP/IP stacks, and low-latency IP-core technologies for network and storage acceleration. Here we share the full technical articles and slides of the up-to-date presentations.

      How Bad is TCP? (And What Are the Alternatives?)

      How Bad is TCP? (And What Are the Alternatives?)

      Sep 20, 20235 months ago

      Presentation at SNIA Storage Developers Conference, Fremont, CA, Sept. 18-21, 2023 Tail latencies in networking tend to worry us all, whether we implement distributed storage and compute or whether we…

      Composable Edge Cloud Systems With NVMe-over-5G URLLC

      Composable Edge Cloud Systems With NVMe-over-5G URLLC

      Mar 14, 202312 months ago

      Presentation at Embedded World 2023, Nuremberg, Germany 5G Radio addresses machine-type communication with low energy demands. 5G Edge Clouds reduce processing latency by bringing extra compute close to the “edge”.…

      Converging PCIe and TSN Ethernet for Composable Infrastructure in High-Performance In-Vehicle Embedded Systems

      Converging PCIe and TSN Ethernet for Composable Infrastructure in High-Performance In-Vehicle Embedded Systems

      Aug 22, 20222 years ago

      Presentation at SNIA Storage Developers Conference, San Jose, Sept. 12-15, 2022 Costs and risks of implementing High-Performance Embedded Systems such as Centralized Car Servers for Autonomous Vehicles can be reduced…

      10 GigE TCP/IP Stack for High-Speed Camera Transport

      10 GigE TCP/IP Stack for High-Speed Camera Transport

      Jul 7, 20222 years ago

      Presentation at FPGA Conference Europe in Munich, Germany, July 5-7, 2022 MLE presents NPAP, a TCP/IP full accelerator from Fraunhofer HHI, for use in Multi-Gigabit High-Speed Camera Image Transport. With…

      Zone-Based Automotive-Backbones

      Zone-Based Automotive-Backbones

      Jun 1, 20222 years ago

      Presentation at Automotive Ethernet Congress in Munich, Germany, June 1-2, 2022 Fraunhofer IPMS and MLE present a joint work on how to combine TSN Ethernet and TCP/IP as an ultra-reliable…

      Platform Choices for FPGA-Based In-Network Compute Acceleration

      Platform Choices for FPGA-Based In-Network Compute Acceleration

      Apr 28, 20222 years ago

      Presentation at SmartNICsSummit 2022, April 26-28, 2022 FPGA-based SmartNICs can provide significant benefits by offloading network data processing off of CPU cores, data-in-motion processing, effectively enabling In-Network Compute. However, FPGA…

      CORUNDUM – From a NIC to a Platform for In-Network Compute

      CORUNDUM – From a NIC to a Platform for In-Network Compute

      Jan 30, 20222 years ago

      Presentation at FOSDEM’22, February 5-6, 2022 This joint presentation between Alex Forencich, UC San Diego, and Ulrich Langenbach, MLE, provides an introduction to the corundum project, implementing a 100 GbE…

      Zone-Based Automotive Backbones Tunneling PCIe

      Zone-Based Automotive Backbones Tunneling PCIe

      Jun 1, 20213 years ago

      Presentation at PCI-SIG Virtual Developers Conference 2021, May 25-26 The need for more safe and eco-friendly vehicles drives automotive connectivity towards so-called Zone-Based Architectures. Inside those so-called Zone Gateways PCIe…

      PCIe-over-TCP-over-TSN-over-10/25GigE

      PCIe-over-TCP-over-TSN-over-10/25GigE

      Sep 24, 20203 years ago

      Presentation at 4th Workshop “Programmable Processing for the Autonomous / Connected Vehicle”, Sept. 24, 2020 at TH Ulm, Germany ADAS and Autonomous Driving push the migration towards Zone-based architectures, which…

      Security / Trusted Execution Environment and Functional Safety with Zync Ultrascale+ MPSoC / RFSoC

      Security / Trusted Execution Environment and Functional Safety with Zync Ultrascale+ MPSoC / RFSoC

      Jul 17, 20195 years ago

      Presentation at the Workshop Programmable Processing for the Autonomous / Connected Vehicle 2019 in Neu-Ulm The security of Embedded Systems has become a key concern, especially when hacked or tampered…

      Resources

      Resources

      Here you can find helpful information, links and material on:

      Online Demo      |      Technical Publications      |      Application Notes      |      Discontinued Product Support

      Technical Publications

      MLE has been invited to numerous international seminars and webinars to share our experience in FPGA development using advanced PCI Express, TCP/UDP/IP Network Protocol Accelerator Platforms (NPAP), and low-latency IP-core technologies. Full technical articles and slides of the presentations are available here.

      Linux Cross Reference

      LXR (formerly “the Linux Cross Referencer”) is a software toolset for indexing and presenting source code repositories. LXR was initially targeted at the Linux source code, but has proved usable for a wide range of software projects. MLE provides this service to everybody interested on MLE’s LXR.

      Application Notes

      MLE is professional in building the prototyping system for short Time-to-Market projects, analyzing and improving latency in a network protocol processing system, and accelerating algorithms and communication protocols based on FPGA. MLE’s research for applications in Deterministic Networking, Streaming Data Storage, and I/O Connectivity is shared in MLE DevZone Application Notes.

      User Guide

      Xilinx Wiki page Almost all user documentation for MLE’s products and solutions are available online.

      Products co-developed with Xilinx, such as the Zynq SATA Storage Extension, can be found on the Xilinx Wiki page.

      Documentation for the MLE internally developed products can be found in MLE’s Developer Zone.

      Virtual Patent Marking

      Virtual Patent Marking

      Missing Link Electronics, Inc. (MLE) is a provider of Semiconductor Intellectual Property Cores (IP Cores) and electronic subsystems. MLE’s technology is used in products and licensable solutions and system stacks sold, which are offered by MLE and by commercial partners.

      This page is intended to serve as notice under 35 U.S.C. § 287(a).

      The following patents apply to MLE products:

      MLE ProductPatents
      Auto/TSNUS Patent No. 9,209,828
      US Patent No. 10,708,199
      US Patent No. 10,848,442
      US Patent No. 11,356,388
      US Patent No. 11,695,708
      Other Patents Pending
      PCIe Long-Range TunnelUS Patent No. 10,708,199
      US Patent No. 10,848,442
      US Patent No. 11,356,388
      US Patent No. 11,695,708
      Other Patents Pending
      NVMe/TCP IP CoreUS Patent No. 10,708,199
      US Patent No. 10,848,442
      US Patent No. 11,356,388
      US Patent No. 11,695,708
      Other Patents Pending
      PCIe Non-Transparent Bridge (NTB)US Patent No. 10,708,199
      US Patent No. 10,848,442
      US Patent No. 11,356,388
      US Patent No. 11,695,708
      Other Patents Pending
      Soft ADCUS Patent No. 10,140,049
      US Patent No. 10,509,880
      Other Patents Pending
      Soft DACUS Patent No. 10,140,049
      US Patent No. 10,509,880
      Other Patents Pending

      Composable Edge Cloud Systems With NVMe-over-5G URLLC

      Presentation at Embedded World 2023, Nuremberg, Germany

      5G Radio addresses machine-type communication with low energy demands. 5G Edge Clouds reduce processing latency by bringing extra compute close to the “edge”. To be cost efficient, Edge Cloud systems are implemented following modern datacenter technology, such as NVMe. NVMe uses PCIe. PCIe typically is implemented for short-range up to 30 cm but for composability, there is so-called NVMe-over-Fabric built on top of PCIe Long-Range Tunnel.

      With 3GPP Release 15 5G Radio starts meeting the requirements for implementing such PCIe Long-Range Tunnel, enabling the design of composable Edge Cloud Storage over 5G. Our presentation at Embedded World 2023 demonstrates a proof-of-concept “NVMe-over-5G” implementation along with a methodology for detailed latency analysis. We start with key aspects of 5G URLLC, PCIe and Long-Range PCIe, followed by introducing NVMe and composable Datacenter architectures. We then present our setup NVMe-over-5G running on the experimental 5G system at Fraunhofer and TU Berlin. We use COTS hardware comprising AMD/Xilinx Ultrascale+ MPSoC and 5G modems to connect a standard NVMe SSD with a standard CPU running Linux and the NVMe protocol. We discuss latency numbers, i.e. how much each intermediate component contributes to the total PCIe NVMe end-to-end latency. Our findings show that in general 5G URLLC can meet the PCIe/NVMe requirements, as long as certain optimizations are implemented, to reduce tail-end latency.

      Converging PCIe and TSN Ethernet for Composable Infrastructure in High-Performance In-Vehicle Embedded Systems

      Presentation at SNIA Storage Developers Conference, San Jose, Sept. 12-15, 2022

      Costs and risks of implementing High-Performance Embedded Systems such as Centralized Car Servers for Autonomous Vehicles can be reduced when borrowing from modern datacenter technology. Therefore, PCIe and Multi-Gigabit Ethernet have become a foundation for automotive in-vehicle infrastructure. Together with partner Fraunhofer IPMS, MLE describes the needs of modern automotive networking and storage architectures, and will share approaches for converging (real-time) Ethernet and PCIe as a common fabric for reliable and cost-efficient implementations. First performance results of a proof-of-concept implementation are shown.

      10 GigE TCP/IP Stack for High-Speed Camera Transport

      Presentation at FPGA Conference Europe in Munich, Germany, July 5-7, 2022

      MLE presents NPAP, a TCP/IP full accelerator from Fraunhofer HHI, for use in Multi-Gigabit High-Speed Camera Image Transport. With increasing resolution and faster frame-rates in cameras and other image sensors, current standards such as GigEVision are running out of steam. Furthermore, modern “down-stream” image processing based on Artificial Intelligence relies on loss-less transport of pixels, lines and entire image frames. This presentation goes into the details of TCP/IP as a reliable, loss-less transport and closes with an implementation example using MicroChip PolarFire FPGA.