Request Information for PCIe Connectivity Subsystems

PCIe Connecivity

PCIe Long-Range Tunnel

Based on a combination of network protocol acceleration technology from German Fraunhofer HHI and patented technology from MLE you can now extend the range of your PCIe connectivity well beyond the 12 inches supported by the standard and without the need to costly PCIe cables.

The fundamental concept behind is to transport PCIe Transaction Layer Packets (TLP) via TCP/IP, all implemented as a digital circuit in ASIC or FPGA. This guarantees reliable delivery and very deterministic delivery times. Optionally, this can be complemented by using real-time Ethernet such as AVB or TSN.

Our PCIe Long-Range Tunnel subsystem supports the Xilinx PCIe hard-IP as well as soft-IP cores XpressRICH Controller IP for PCIe 3.1/3.0 (or newer) from PLDA or the Expresso Core from Northwest Logic / Rambus.