NPAP is the TCP/UDP/IP Full Accelerator from Fraunhofer HHI which enjoys production use in FPGA applications for automotive, industrial, medical, robotics, test & measurement and wired/wireless communications.
At AMD’s 2025 EMEA Signal Processing Working Group on Oct. 29-31 at AMD Dublin, Ireland, MLE presented the newest storage acceleration technology: theNVMe Fast FPGA RAID (FFRAID).
With MLE NVMe FFRAID you can transfer, gapless and loss-less, bulky data from multiple sensors to a RAID of NVMe SSDs at aggregated speeds up to 400 Gbps. Multiple systems can further be cascaded via IEEE 1588-2019 (HA) Precision Time Synchronization (PTP) for faster and/or deeper recording.
MLE NVMe FFRAID implements a channel-based architecture where each data source/sink can be associated with a dedicated RAID engine and a dedicated storage space.
▲ MLE NVMe FFRAID implements a channel-based architecture
Key Features
Scalable from 100Gbps to 400Gbps
Cascade of multiple systems with time-synchronization
Start-Pause-Stop Data Recording
Pre-trigger Data Recording using circular buffers
Adaptable signal front-ends
Striping mode (RAID 0)
Striped and mirrored mode (RAID 0+1)
Read/write compatible with Linux Software-RAID
Compatible with TGC OPAL
Applications
Autonomous Vehicle Path Record & Replay
Automotive / Medical / Industrial Test Equipment
Broadcast Recording
High-speed Radar / Lidar / Camera Data Acquisition & Storage
Network Telemetry and Analytics
Very Deep Network Packet Capture of Ethernet or IPv4 or TCP/UDP Data
Modern Software-Defined Vehicle (SDV) architectures are pushing automotive in-vehicle networks towards more bandwidth and lower, guaranteed transport latency.
In the Symposium, work presented is intermediate results from joint research project “CeCaS,” which is co-funded by the German Bundesministerium für Forschung, Technologie und Raumfahrt. We will also showcase how MLE and partner Trenz Electronic put together an Automotive Rapid Prototyping System (Auto/RPS) based on AMD’s Versal Edge AI devices to swiftly building the automotive networks in the CeCaS project.
Date: Wed-Thu Oct 8-9, 2025
Location: Hotel Vier Jahreszeiten Kempinski, Munich, Germany
MLE Robo/TSN converges OT and IT networks and, thereby, enables virtualized PLCs in a Factory Cloud via secure “tunnels” to transport existing OT fieldbus protocols over standard IEEE TSN Ethernet. MLE Robo/TSN was recently featured in two articles from CODESYS GmbH:
The CODESYS Group ranks among the world’s leading software manufacturers in the automation industry. The company´s main focus is the development and distribution of CODESYS, the well-known integrated IEC 61131-3 development environment (IDE) for controller applications and CODESYS Control, the platform independent runtime system.
CC-Link, short for Control and Communications Link, is a widely adopted fieldbus system used in industrial automation. The CC-Link Partner Association (CLPA), based in Japan, is dedicated to promoting the CC-Link fieldbus industrial network in response to recent needs for control system optimization.
MLE has joined CLPA to facilitate the integration of CC-Link IE (Industrial Ethernet) and Time-Sensitive Networking (TSN)—advancing next-generation industrial networking solutions that are faster, more synchronized, and ready for the future of automation.
Missing Link Electronics (MLE) is now a partner of Lattice Semiconductor, providing a range of pre-validated FPGA IP cores and licensable system stacks optimized for Lattice FPGAs. This collaboration is aimed at accelerating the design projects of Lattice FPGA users with proven, ready-to-integrate solutions.
By combining MLE’s optimized subsystems with Lattice’s low-power, mid-range FPGAs, customers gain a streamlined path to robust networking solutions across a wide range of sectors, including communications, computing, industrial, and automotive applications.
MLE’s application-specific solutions integrate subsystem stacks with the new Multi-Gigabit Lattice FPGAs to deliver real-time communication for industrial connectivity and automotive networking.
GNSS is widely used for positioning and synchronization—particularly in applications, such as vehicles and drones, where merging recorded radar data and coordinating multiple nodes over-the-air is essential. Accurate time-stamping is crucial to ensure data integrity, which requires a reliable and common time source. However, GNSS connectivity can be limited or completely unavailable in challenging environments like tunnels or urban canyons, making precise synchronization difficult.
In this presentation, MLE showcases our approach to synchronize devices using PTP-based application layer time synchronization over 5G sidelink. We walk through the approach and implications of correlating PTP messages with 5G PHY layer frame timing, and briefly touch on a method for further improving the timestamp accuracy. In the end, we present our proof-of-concept demonstrator setup developed in collaboration with Fraunhofer HHI, along with initial experimental results, demonstrating microsecond-level time synchronization accuracy via PTP over 5G sidelink. Notably, this approach relies purely on existing mechanisms and requires no additional modifications to future 6G standards.
In the decade of high-performance networking and computing, FPGAs have arisen as a promising and highly convenient solution, offering flexibility, reprogramming capacity and parallelism options. The role of high-performance solutions that offer a high throughput in network-related operations is extremely beneficial in real-time processing tasks executed on embedded systems, such as real-time video streaming.
This presentation showcases the capabilities and obtained performance of our FPGA-based high-speed multi GMSL camera to RTP streaming solution using a single 10GbE link. There will be a walk through the multi GMSL Ser/Des integration, and the FPGA-powered components overview: the CSI-2 to RTP streams translation and the multi-GMSL camera synchronization, accompanied by the highly configurable and low-latency UDP/IP network accelerator. The described high-performance data path is integrated with the on-chip CPU subsystem to provide time synchronization via PTPv2 and enable control and monitoring of the device via the network. At the end of the presentation, we emphasize the most important design choices to build such a multi-camera streaming system. We finally draw the conclusions and the lessons learned from that successful experience.
Date: Thursday July 3rd, 2025
Track 2 – Embedded / Vision (starts at 1:30pm CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join MLE and Analog Devices at FPGA Conference 2025 to discover how we built the highly configurable and low-latency Multi GMSL Camera for 10GbE RTP Streaming!
Enter the promo code FPGA25-CON-MEETME to get 20% discount on all tickets!
Automotive architectures are transforming: while more and more sensors become integrated in vehicles, the automotive industry is looking for ways to reduce wiring efforts in production, more scalability, higher level of integration and faster ways development.
Auto/TSN stands for automotive data over Time-Sensitive Networks which is an in-vehicle network infrastructure based on open standards such as IEEE Ethernet.
Auto/TSN virtualizes the in-vehicle network infrastructure: Key objective is to reduce costs, increase scalability and enable upgradability for next-generation automotive architectures including electric and/or autonomous vehicles.
The presentation will show how a zone based architecture can look like in comparison to the “classic” wiring. It will explain the tasks of a zone gateway and why FPGA/Soc play a major role in sensor fusion. Further more why it is important to use middleware which turns devices in a service for a central car server and other ECUs. For visualization, we will show examples of the government funded CeCaS research project and show the complete chain from camera sensors over zone gateways to the central car server.
Date: Thursday July 3rd, 2025
Track 1 – Application (starts at 11:50am CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join us at FPGA Conference 2025 to learn more details about the automotive zone-based architecture with TSN technology!
Enter the promo code FPGA25-CON-MEETME to get 20% discount on all tickets!
