CC-Link, short for Control and Communications Link, is a widely adopted fieldbus system used in industrial automation. The CC-Link Partner Association (CLPA), based in Japan, is dedicated to promoting the CC-Link fieldbus industrial network in response to recent needs for control system optimization.
MLE has joined CLPA to facilitate the integration of CC-Link IE (Industrial Ethernet) and Time-Sensitive Networking (TSN)—advancing next-generation industrial networking solutions that are faster, more synchronized, and ready for the future of automation.
Missing Link Electronics (MLE) is now a partner of Lattice Semiconductor, providing a range of pre-validated FPGA IP cores and licensable system stacks optimized for Lattice FPGAs. This collaboration is aimed at accelerating the design projects of Lattice FPGA users with proven, ready-to-integrate solutions.
By combining MLE’s optimized subsystems with Lattice’s low-power, mid-range FPGAs, customers gain a streamlined path to robust networking solutions across a wide range of sectors, including communications, computing, industrial, and automotive applications.
MLE’s application-specific solutions integrate subsystem stacks with the new Multi-Gigabit Lattice FPGAs to deliver real-time communication for industrial connectivity and automotive networking.
GNSS is widely used for positioning and synchronization—particularly in applications, such as vehicles and drones, where merging recorded radar data and coordinating multiple nodes over-the-air is essential. Accurate time-stamping is crucial to ensure data integrity, which requires a reliable and common time source. However, GNSS connectivity can be limited or completely unavailable in challenging environments like tunnels or urban canyons, making precise synchronization difficult.
In this presentation, MLE showcases our approach to synchronize devices using PTP-based application layer time synchronization over 5G sidelink. We walk through the approach and implications of correlating PTP messages with 5G PHY layer frame timing, and briefly touch on a method for further improving the timestamp accuracy. In the end, we present our proof-of-concept demonstrator setup developed in collaboration with Fraunhofer HHI, along with initial experimental results, demonstrating microsecond-level time synchronization accuracy via PTP over 5G sidelink. Notably, this approach relies purely on existing mechanisms and requires no additional modifications to future 6G standards.
In the decade of high-performance networking and computing, FPGAs have arisen as a promising and highly convenient solution, offering flexibility, reprogramming capacity and parallelism options. The role of high-performance solutions that offer a high throughput in network-related operations is extremely beneficial in real-time processing tasks executed on embedded systems, such as real-time video streaming.
This presentation showcases the capabilities and obtained performance of our FPGA-based high-speed multi GMSL camera to RTP streaming solution using a single 10GbE link. There will be a walk through the multi GMSL Ser/Des integration, and the FPGA-powered components overview: the CSI-2 to RTP streams translation and the multi-GMSL camera synchronization, accompanied by the highly configurable and low-latency UDP/IP network accelerator. The described high-performance data path is integrated with the on-chip CPU subsystem to provide time synchronization via PTPv2 and enable control and monitoring of the device via the network. At the end of the presentation, we emphasize the most important design choices to build such a multi-camera streaming system. We finally draw the conclusions and the lessons learned from that successful experience.
Date: Thursday July 3rd, 2025
Track 2 – Embedded / Vision (starts at 1:30pm CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join MLE and Analog Devices at FPGA Conference 2025 to discover how we built the highly configurable and low-latency Multi GMSL Camera for 10GbE RTP Streaming!
Enter the promo code FPGA25-CON-MEETME to get 20% discount on all tickets!
Automotive architectures are transforming: while more and more sensors become integrated in vehicles, the automotive industry is looking for ways to reduce wiring efforts in production, more scalability, higher level of integration and faster ways development.
Auto/TSN stands for automotive data over Time-Sensitive Networks which is an in-vehicle network infrastructure based on open standards such as IEEE Ethernet.
Auto/TSN virtualizes the in-vehicle network infrastructure: Key objective is to reduce costs, increase scalability and enable upgradability for next-generation automotive architectures including electric and/or autonomous vehicles.
The presentation will show how a zone based architecture can look like in comparison to the “classic” wiring. It will explain the tasks of a zone gateway and why FPGA/Soc play a major role in sensor fusion. Further more why it is important to use middleware which turns devices in a service for a central car server and other ECUs. For visualization, we will show examples of the government funded CeCaS research project and show the complete chain from camera sensors over zone gateways to the central car server.
Date: Thursday July 3rd, 2025
Track 1 – Application (starts at 11:50am CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join us at FPGA Conference 2025 to learn more details about the automotive zone-based architecture with TSN technology!
Enter the promo code FPGA25-CON-MEETME to get 20% discount on all tickets!
For the AMD Technology Day in Gothenburg, Sweden, MLE presented an automotive rapid prototyping system for architecture exploration and development of future Zone based automotive architectures. The outcome presented based on a practical example of work done in the MANNHEIM CeCaS Project.
The national funded research project MANNHEIM CeCaS (Central Car Server) was initiated between industry and academia, focusing on the creation of fundamental hardware and software building blocks for next-generation automotive technology. Key innovations span from chip technology & HW acceleration, E/E architecture & topology, to networking & communication, software architecture & abstraction, housing & cooling, as well as methodologies like AI-based system modelling and HW/SW co-design.
NPAP is the TCP/UDP/IP Full Accelerator from Fraunhofer HHI which enjoys production use in FPGA applications for automotive, industrial, medical, robotics, test & measurement and wired/wireless communications.
Newly introduced features include built-in diagnostics plus functionality to emulate Network Impairment.
Also added was support for the new Agilex 5E FPGA devices from Altera where MLE NPAP integrates with the GTS Ethernet Intel® FPGA Hard IP.
PCO, an Excelitas Technologies® Corp. brand, is a leading specialist and Pioneer in Cameras and Optoelectronics with more than 30 years of expert knowledge and experience of developing and manufacturing high-end imaging systems. The company’s cutting edge sCMOS and high-speed cameras are used in scientific and industrial research, automotive testing, quality control, metrology and a large variety of other applications all over the world.
PCO has licensed MLE’s FFRAID for use in optimized recording systems that complement PCO’s high-speed cameras.
The recorder is equipped with a high-performance SSD tray, providing fast data storage with a capacity of up to 8 TB. It supports the simultaneous connection of 1 to 8 cameras and features a 25G Ethernet connection for efficient data transfer to a PC. The system offers flexible recording modes, including Record, Pause, Play, and Circular Buffer Recording, ensuring versatile operation for various applications.
At Embedded World 2025 in Nuremberg Exhibition from March 11-13 in Nuremberg, Germany, Analog Devices (ADI: Hall 4A: Stand 360) and Missing Link Electronics (MLE: Hall 5: Stand 140) will be sharing solutions that are redefining high-speed Ethernet connectivity. Together, they are paving the way for the next generation of embedded applications across various markets ranging from automotive to industrial automation to IoT.
Mark your calendar to make a stop at the ADI booth to see the “High-Performance Analog Meets AI” demo. This demo dives into the shift from traditional signal processing to AI-driven flows and speaks to the trend of extracting data from high-performance, high-data-rate analog signal chains for AI model training and real-time inference.
The demo shows how ADI’s data extraction framework, built on top of open-source software, open-source FPGA infrastructure, and scalable host-side data management flows, can be used in conjunction with ADI’s high-performance transceivers and converters to streamline the development and deployment of AI-capable and intelligent edge systems.
MLE helps ADI implement Corundum – an open-source, high-performance FPGA-based NIC and platform – on the ADRV9009-ZU11EG System on Module (see ADRV9009-ZU11EG RF-SOM Hardware Overview). Via Linux NAPI, the standard open source Linux network stack, data is captured in system memory and then streamed to the Nvidia IGX/Host PC for AI processing.
Learn more about how MLE enables high performance analog for AI processing and at ADI’s EZ Blog.
High-performance data extraction architecture for AI model training and real-time inference in high-data-rate analog signal chains
MLE helps ADI implement Corundum on the ADRV9009-ZU11EG System on Module
