MLE will present "Zone-Based Architectures with Auto/TSN on Zynq UltraScale+ MPSoC" at the Xilinx Adapt EMEA: Automotive. This is organized as a Virtual Technical Event in the mornings of May 18-19, 2021.
MLE participated as sponsor and as a presenter of “Zone-Based Automotive Backbones Tunneling PCIe” at the PCI-SIG Virtual Developers Conference 2021.
(download slides) or visit our technical publications
Algoblu announced today its Network Element Virtualization (NEV) platform that virtualizes and orchestrates underlying network resources to help carriers offer more application-oriented customized services to both commercial and residential customers. Thanks to the new FPGA-based technology, the cost per bit decreases by more than four times and operation efficiency increases three times.
“We are pleased to collaborate with Algoblu to develop a Network Element Virtualization chip built on leading-edge FPGA technology. The chip is key to Algoblu’s NEV architecture with an FPGA-based SMartNIC, all developed in an elegant way,” says Dr. Endric Schubert, CTO at Missing Link Electronics.
PCI Express (PCIe) has significant advantages which help to drive innovation towards more eco-friendly and safer vehicles. MLE is a member of PCI-SIG and has been providing technology and solutions for PCIe-based Long-Range Tunneling used for automotive backbone connectivity and is proud to volunteer for PCI-SIG's newly formed Automotive Workgroup.
MLE presents “Deterministic Networking with TCP-TSN-Cores for 10/25/50/100 Gigabit Ethernet” in Technical Brief MLE-TB20201203.
We all observe a growing need to connect computers with each other with shorter delays (i.e. lower latencies) and higher bandwidth, in particular for High-Performance Computing (HPC) in the data center and in embedded systems such as advanced industrial robotics or autonomous vehicles, requiring the so-called deterministic networking. Processing of TCP/IP based network protocols at speeds of 10 Gbps and beyond demand kernel bypass solutions (such as Intel’s DPDK or Solarflare’s/Xilinx’ Onload or Mellanox/NVida VMA) and/or so-called TOEs (TCP Offload Engines).
Domain-Specific Architectures (DSA) use so-called heterogeneous computing elements, also known as Cores with the objective to put the compute burden where it belongs. This is a well established approach going back to the early days when an x86 CPU was partnered with an x87 for better floating-point processing. Today, it is common to deploy various flavors of Cores, for example:
This is because such (special purpose) fixed-function or programmable function accelerator Cores are optimized for a particular domain and, when properly used, not only take processing load off the (general purpose) CPU but also deliver better overall performance (which is data processed per time) and better efficiency (which is performance per Watt).
Over the following pages we will make a case for processing TCP/IP over TSN over 10/25/50/100 Gigabit Ethernet on dedicated Cores which has significant advantages in particular for real-time Ethernet and Deterministic Networking. These so-called TCP-TSN-Cores can be integrated either in FPGAs or in SoCs (ASIC and ASSP). As we will show, TCP-TSN-Cores are more than just a TOE – the commonly used approach for network protocol acceleration. By running the entire network protocol stack from OSI Layer 2 to at least Layer 4 in a dedicated integrated circuit – a so-called Full Accelerator – we can remove (general purpose) CPUs entirely from the datapath.
Hence, TCP-TSN-Cores can deliver very low bounded and deterministic latency with predictable scalability needed for 10/25/50/100 Gigabit Deterministic Networking.
Missing Link Electronics has been awarded US Patent 10,848,442 on Heterogeneous Packet-Based Transport which covers aspects of secure tunneling packets such as PCI Express (PCIe) Transaction-Layer Packets (TLP) over reliable TCP/IP over 1/10/25/50/100G Ethernet. This extends the range of PCIe and enables building distributed systems based on PCIe.
MLE publishes Technical Brief MLE-TB20201012 “Sustained, High-Speed Data Recording with NVMe SSDs” discussing read/write performance aspects of various NVMe SSDs.
MLE presents "PCIe-over-TCP-over-TSN-over10/25GigE" at the 4th Workshop "Programmable Processing for the Autonomous / Connected Vehicle".
This workshop was hosted by Technische Hochschule Ulm (THU) on September 24, 2020.
Click here to see the slides of the presentation.
MLE updates NVMe Streamer a so-called Full Accelerator NVMe host subsystem integrated into Xilinx FPGAs. This update covers new NVMe SSD features such as changes in default page size and performance enhancements to support maximum bandwidth for modern PCIe Gen3 x4 m.2 SSD.